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參數(shù)資料
| 型號(hào)： | ICS541MT |
| 英文描述： | PRELIMINARY INFORMATION PLL Clock Divider |
| 中文描述： | 初步資料PLL時(shí)鐘分頻器 |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大小： | 59K |
| 代理商： | ICS541MT |
ICS541
PLL Clock Divider
MDS 541 B
Integrated Circuit Systems, Inc. 525 Race Street San JoseCA 95126 (408)295-9800tel www.icst.com
1
Revision 082500 Printed 11/14/00
PRELIMINARY INFORMATION
Packaged in 8 pin SOIC
Low cost clock divider
Low skew (500ps) outputs. One is ÷ 2 of other.
Easy to use with other generators and buffers
Input clock frequency up to 135 MHz at 3.3 V
Input clock frequency up to 156 MHz at 5.0 V
Tolerant of poor input clock duty cycle, jitter.
Output clock duty cycle of 45/55
Power Down turns off chip
Output Enable
Full CMOS clock swings with 25mA drive
capability at TTL levels
Advanced, low power CMOS process
Operating voltages of 3.0 to 5.5 V
The ICS541 is a cost effective way to produce a
high quality clock output divided from a clock
input. The chip accepts a clock input up to
135 MHz at 3.3 V, and by using proprietary Phase
Locked Loop (PLL) techniques, produces a divide
by 1, 2, 4, or 8 of the input clock. There are two
outputs on the chip, one being a low-skew divide
by two of the other. So, for instance, if an 80 MHz
input clock is used, the ICS541 can produce low
skew 80 MHz and 40 MHz clocks, or 40 MHz
and 20 MHz clocks, or 20 MHz and 10MHz
clocks. The chip has an all-chip power down mode
that stops the outputs low, and an OE pin that tri-
states the outputs.
The ICS541 is a member of the ICS
ClockBlocks family of clock building blocks.
See the ICS542 and ICS543 for other clock
dividers, and the ICS300, 501, 502, and 503 for
clock multipliers.
Block Diagram
Description
Features
PLL,
Divider and
Selection
Circuitry
VDD GND
CLK
Output
Buffer
Output
Buffer
S1, S0
2
÷2
Input Clock
OE (both outputs)
CLK/2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS541 | 4.7K OHM 1/8W 5% SMT RESISTOR |
| ICS541M | PRELIMINARY INFORMATION PLL Clock Divider |
| ICS542MT | Clock Divider |
| ICS542M | Clock Divider |
| ICS542 | Clock Divider |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS542 | 制造商:ICS 制造商全稱:ICS 功能描述:Clock Divider |
| ICS542-DPK | 制造商:Integrated Device Technology Inc 功能描述:IC DIVIDER USER CONFIG 8-SOIC |
| ICS542M | 功能描述:IC CLOCK BUFF DIVIDER 1:2 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復(fù)用器 電路數(shù):1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無(wú) 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| ICS542MI | 功能描述:IC CLOCK BUFF DIVIDER 1:2 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復(fù)用器 電路數(shù):1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無(wú) 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| ICS542MILF | 功能描述:IC CLOCK BUFF DIVIDER 1:2 8-SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:- 產(chǎn)品培訓(xùn)模塊:High Bandwidth Product Overview 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:4 差分 - 輸入:輸出:是/是 輸入:CML，LVDS，LVPECL 輸出:CML 頻率 - 最大:2.5GHz 電源電壓:2.375 V ~ 2.625 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) |
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