參數(shù)資料
型號(hào): ICS525-01RT
英文描述: XTAL CER SMT 6X3.5 2PAD
中文描述: 奧斯卡⑩用戶可配置時(shí)鐘
文件頁(yè)數(shù): 7/8頁(yè)
文件大?。?/td> 70K
代理商: ICS525-01RT
ICS525-01/02
OSCaR User Configurable Clock
MDS 525-01/02 I
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126(408) 295-9800tel www.icst.com
7
Revision 071100 Printed 11/13/00
Parameter
AC CHARACTERISTICS (VDD = 3.3 V unless otherwise noted)
Input Frequency, crystal input
Input Frequency, clock input
Output Frequency, VDD = 4.5 to 5.5V
ICS525-01, note 1
Output Frequency, VDD = 3.0 to 3.6V
ICS525-01, note 1
Output Frequency, VDD = 4.5 to 5.5V
ICS525-02, note 1
Output Frequency, VDD = 3.0 to 3.6V
ICS525-02, note 1
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle, OD = 2, 4, 6, 8, or 10
Output Clock Duty Cycle, OD = 3, 5, 7, or 9
Output Clock Duty Cycle, OD = 1 (-02 only)
Power Down Time, PD low to clocks stopped
Power Up Time, PD high to clocks stable
Absolute Clock Period Jitter, ICS525-01, Note 2
One Sigma Clock Period Jitter, ICS525-01, Note 2 One Sigma
Absolute Clock Period Jitter, ICS525-02, Note 2
One Sigma Clock Period Jitter, ICS525-02, Note 2 One Sigma
Conditions
Minimum
Typical
Maximum
Units
5
27
50
160
140
100
90
MH z
MH z
0.5
1
1
1
1
0 °C to 70 °C
-40 °C to +85 °C
0 °C to 70 °C
-40 °C to +85 °C
MH z
MH z
-40 °C to +85 °C
1.5
250
MH z
-40 °C to +85 °C
0.8 to 2.0V
2.0 to 0.8V
at VDD/2
at VDD/2
at VDD/2
1
200
55
60
65
50
10
MH z
ns
ns
%
%
1
1
45
40
35
49 to 51
ns
ms
ps
ps
ps
ps
Deviation from mean
±140
45
±85
30
Deviation from mean
Electrical Specifications (cont.)
Note 1:
The phase relationship between input and output can change at power up. For a fixed phase
relationship see the ICS527.
Note 2:
For 16 MHz input, 100 MHz output. Use the -02 for lowest jitter.
相關(guān)PDF資料
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