參數(shù)資料
型號: ICS514
英文描述: LOCO⑩ PLL Clock Generator
中文描述: 本地⑩PLL時鐘發(fā)生器
文件頁數(shù): 4/4頁
文件大?。?/td> 42K
代理商: ICS514
ICS514
LOCO PLL Clock Generator
MDS 514 B
Integrated Circuit Systems 525 Race Street San JoseCA 95126 (408)295-9800tel (408)295-9818fax
4
Revision 080699
Printed 11/13/00
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does
not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
Package Outline and Package Dimensions
Inches
Min
0.055
0.013
0.185
0.150
0.225
.050 BSC
Millimeters
Min
1.397
0.330
4.699
3.810
5.715
1.27 BSC
Symbol
A
b
D
E
H
e
h
L
Q
Max
0.068
0.019
0.200
0.160
0.245
Max
1.7272
0.483
5.080
4.064
6.223
0.015
0.035
0.01
0.381
0.889
0.254
0.016
0.004
0.406
0.102
8 pin SOIC
Ordering Information
Part/Order Number
ICS514M
ICS514MT
Marking
ICS514M
ICS514M
Package
8 pin SOIC
Temperature
0-70°C
0-70°C
8 pin SOIC on tape and reel
External Components / Crystal Selection
The ICS514 requires a 0.01μF decoupling capacitor to be connected between VDD and GND. It must be
connected close to the ICS514 to minimize lead inductance. No external power supply filtering is required
for this device. A 33
terminating resistor can be used next to the CLK and REF pins. The total on-chip
capacitance is approximately 12 pF, so a parallel resonant, fundamental mode crystal should be used. For
crystals with a specified load capacitance greater than 12 pF, crystal capacitors should be connected from
each of the pins X1 and X2 to Ground as shown in the Block Diagram on page 1. The value (in pF) of
these crystal caps should be = (CL-12)*2, where CL is the crystal load capacitance in pF. These external
capacitors are only required for applications where the exact frequency is critical. For a clock input,
connect to X1 and leave X2 unconnected (no capacitors on either).
c
A
b
D
E
H
e
h x 45°
Q
Pin 1
LOCO is a trademark of ICS
L
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