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參數(shù)資料
| 型號： | ICS503MT |
| 英文描述： | LOCO⑩ PLL Clock Multiplier |
| 中文描述： | 本地⑩PLL時鐘乘法器 |
| 文件頁數(shù)： | 4/4頁 |
| 文件大?。?/td> | 60K |
| 代理商： | ICS503MT |
ICS503
LOCO PLL Clock Multiplier
MDS 503 A
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126(408) 295-9800tel www.icst.com
4
Revision 111000
PRELIMINARY INFORMATION
While the information presented herein has been checked for both accuracy and reliability, ICS/MicroClock assumes no responsibility for either its use or for the infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS/MicroClock. ICS/MicroClock reserves the right to change any circuitry or specifications without notice. ICS/MicroClock
does not authorize or warrant any ICS/MicroClock product for use in life support devices or critical medical instruments.
Package Outline and Package Dimensions
Inches
Min
0.055
0.013
0.185
0.150
0.225
Millimeters
Min
1.397
0.330
4.699
3.810
5.715
1.27 BSC
0.015
0.01
0.102
Symbol
A
b
D
E
H
e .050 BSC
h
Q
Max
0.068
0.019
0.200
0.160
0.245
Max
1.7272
0.483
5.080
4.064
6.223
0.381
0.254
0.004
8 pin SOIC
Ordering Information
Part/Order Number
ICS503M
ICS503MT
Marking
ICS503M
ICS503M
Package
8 pin SOIC
Temperature
0-70°C
0-70°C
8 pin SOIC on tape and reel
External Components / Crystal Selection
The ICS503 requires a 0.01μF decoupling capacitor to be connected between VDD and GND. It must be
connected close to the ICS503 to minimize lead inductance. No external power supply filtering is required
for this device. A 33
terminating resistor can be used next to the CLK pin. The total on-chip capacitance
is approximately 6 pF, so a parallel resonant, fundamental mode crystal should be used. If exact tuning of
the frequency is required, crystal capacitors should be connected from each of the pins X1 and X2 to
ground as shown in the Block Diagram on page 1. The value (in pF) of these crystal caps should be equal
to (CL-6)*2, where CL is the crystal load capacitance in pF. These external capacitors are only required for
applications where the exact frequency is critical. For a clock input, connect to X1 and leave X2
unconnected (no capacitors on either).
c
A
b
D
E
H
e
h x 45°
Q
Pin 1
LOCO is a trademark of ICS
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