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參數(shù)資料
| 型號： | ICS503MT |
| 英文描述： | LOCO⑩ PLL Clock Multiplier |
| 中文描述： | 本地⑩PLL時(shí)鐘乘法器 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大小： | 60K |
| 代理商： | ICS503MT |
ICS503
LOCO PLL Clock Multiplier
MDS 503 A
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126(408) 295-9800tel www.icst.com
3
Revision 111000
PRELIMINARY INFORMATION
Parameter
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Inputs
Clock Output
Ambient Operating Temperature
Soldering Temperature
Storage temperature
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Operating Voltage, VDD
Input High Voltage, VIH, ICLK only
Input Low Voltage, VIL, ICLK only
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH, CMOS high
Output High Voltage, VOH
Output Low Voltage, VOL
IDD Operating Supply Current, 14 MHz crystal No Load, 80MHz
Short Circuit Current
Input Capacitance, S1, S0
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Input Frequency, crystal input
Input Frequency, clock input
Output Frequency
Output Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
Conditions
Minimum
Typical
Maximum
Units
Referenced to GND
Referenced to GND
Referenced to GND
7
V
V
V
°C
°C
°C
-0.5
-0.5
0
VDD+0.5
VDD+0.5
70
260
150
Max of 10 seconds
-65
3
5.5
V
V
V
V
V
V
V
V
ICLK (Pin 1)
ICLK (Pin 1)
S1, S0
S1, S0
IOH=-4mA
IOH=-25mA
IOL=25mA
(VDD/2)+1
VDD/2
VDD/2
(VDD/2)-1
VDD-0.5
0.5
VDD-0.4
2.4
0.4
16
±70
4
mA
mA
pF
CLK output
Pins 6, 7
See table on page 2
See table on page 2
VDD = 4.5 to 5.5V
VDD = 3.0 to 3.6V
0.8 to 2.0V
2.0 to 0.8V
at VDD/2
Deviation from mean
5
2
14
14
27
50
160
100
55
MHz
MHz
MHz
MHz
ns
ns
%
ps
ps
1
1
45
49 to 51
±120
50
Electrical Specifications
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