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參數(shù)資料
| 型號： | ICS1893BKLF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 88/133頁 |
| 文件大?。?/td> | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 56-VQFN |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 系列： | PHYceiver™ |
| 類型： | PHY 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 56-VFQFP-EP（8x8） |
| 包裝： | 管件 |
| 其它名稱： | 1893BKLF 800-1019 |
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ICS1893BF, Rev. F, 5/13/10
May, 2010
58
Chapter 7 Management Register Set
ICS1893BF Data Sheet - Release
Copyright 2009, IDT, Inc.
All rights reserved.
7.3.2 100Base-TX Full Duplex (bit 1.14)
The STA reads this bit to learn if the ICS1893BF can support 100Base-TX, full-duplex operations. The
ISO/IEC specification requires that the ICS1893BF must set bit 1.14 to logic:
Zero if it cannot support 100Base-TX, full-duplex operations.
One if it can support 100Base-TX, full-duplex operations. (For the ICS1893BF, the default value of bit
1.14 is logic one, in that the ICS1893BF supports 100Base-TX, full-duplex operations.)
Bit 1.14 is a Command Override Write bit, which allows an STA to alter the default value of this bit. [See the
description of bit 16.15, the Command Override Write Enable bit, in Section 7.11, “Register 16: Extended
7.3.3 100Base-TX Half Duplex (bit 1.13)
The STA reads this bit to learn if the ICS1893BF can support 100Base-TX, half-duplex operations. The
ISO/IEC specification requires that the ICS1893BF must set bit 1.13 to logic:
Zero if it cannot support 100Base-TX, half-duplex operations.
One if it can support 100Base-TX, half-duplex operations. (For the ICS1893BF, the default value of bit
1.13 is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the
ICS1893BF supports 100Base-TX, half-duplex operations.)
This bit 1.13 is a Command Override Write bit, which allows an STA to alter the default value of this bit.
[See the description of bit 16.15, the Command Override Write Enable bit, in Section 7.11, “Register 16:
7.3.4 10Base-T Full Duplex (bit 1.12)
The STA reads this bit to learn if the ICS1893BF can support 10Base-T, full-duplex operations. The
ISO/IEC specification requires that the ICS1893BF must set bit 1.12 to logic:
Zero if it cannot support 10Base-T, full-duplex operations.
One if it can support 10Base-T, full-duplex operations. (For the ICS1893BF, the default value of bit 1.12
is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the ICS1893BF
supports 10Base-T, full-duplex operations.)
This bit 1.12 is a Command Override Write bit, which allows an STA to alter the default value of this bit.
[See the description of bit 16.15, the Command Override Write Enable bit, in Section 7.11, “Register 16:
7.3.5 10Base-T Half Duplex (bit 1.11)
The STA reads this bit to learn if the ICS1893BF can support 10Base-T, half-duplex operations. The
ISO/IEC specification requires that the ICS1893BF must set bit 1.11 to logic:
Zero if it cannot support 10Base-T, half-duplex operations.
One if it can support 10Base-T, half-duplex operations. (For the ICS1893BF, the default value of bit 1.11
is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the ICS1893BF
supports 10Base-T, half-duplex operations.)
Bit 1.11 of the ICS1893BF Status Register is a Command Override Write bit., which allows an STA to alter
the default value of this bit. [See the description of bit 16.15, the Command Override Write Enable bit, in
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| ICS1893BKLFT | 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893BKT | 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893BRIEF | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893BY-10 | 功能描述:PHYCEIVER LOW PWR 3.3V 64-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893BY-10LF | 功能描述:PHYCEIVER LOW PWR 3.3V 64-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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