參數(shù)資料
型號: ICS1893AFILFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 62/136頁
文件大小: 0K
描述: PHYCEIVER LOW PWR 3.3V 48-SSOP
標準包裝: 1,000
系列: PHYceiver™
類型: PHY 收發(fā)器
規(guī)程: MII
電源電壓: 3.14 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 48-BSSOP(0.295",7.50mm 寬)
供應商設備封裝: 48-SSOP
包裝: 帶卷 (TR)
其它名稱: 1893AFILFT
Chapter 6
Interface Overviews
ICS1893AF, Rev. D 10/26/04
October, 2004
31
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
6.5
Status Interface
The ICS1893AF provides five multi-function configuration pins that report the results of continual link
monitoring by providing signals that are intended for driving LEDs. (For the pin numbers, see Table 9.2.2.)
Note:
1.
During either a power-on reset or a hardware reset, each multi-function configuration pin is an input
that is sampled when the ICS1893AF exits the reset state. After sampling is complete, these pins are
output pins that can drive status LEDs.
2.
A software reset does not affect the state of a multi-function configuration pin. During a software reset,
all multi-function configuration pins are outputs.
3.
Each multi-function configuration pin must be pulled either up or down with a resistor to establish the
address of the ICS1893AF. LEDs may be placed in series with these resistors to provide a designated
status indicator as described in Table 6-3.
Caution:
All pins listed in Table 6-3 must not float.
4.
As outputs, the asserted state of a multi-function configuration pin is the inverse of the sense sampled
during reset. This inversion provides a signal that can illuminate an LED during an asserted state. For
example, if a multi-function configuration pin is pulled down to ground through an LED and a
current-limiting resistor, then the sampled sense of the input is low. To illuminate this LED for the
asserted state, the output is driven high.
5.
Adding 10K
resistors across the LEDs ensures the PHY address is fully defined during slow VDD
power-ramp conditions.
6.
PHY address 00 tri-states the MII interface. (Do not select PHY address 00 unless you want the MII
tri-stated.)
Table 6-3.
Pins for Monitoring the Data Link
Pin
LED Driven by the Pin’s Output Signal
P0AC
AC (Link Activity) LED
P1CL
CL (Collisions) LED
P2LI
LI (Link Integrity) LED
P3TD
TD (Transmit Data) LED
P4RD
RD (Receive Data) LED
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