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| 型號(hào)： | ICS1892Y-10 |
| 英文描述： | 10Base-T/100Base-TX Integrated PHYceiver |
| 文件頁(yè)數(shù)： | 52/148頁(yè) |
| 文件大小： | 816K |
| 代理商： | ICS1892Y-10 |
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ICS1892, Rev. D, 2/26/01
February 26, 2001
52
Chapter 7
Functional Blocks
ICS1892 Data Sheet
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
7.5.9
10Base-T Operation: Jabber
According to the ISO/IEC 8802-3 standard, a jabber function detects abnormally long transmissions and
takes appropriate actions to avoid them. The ICS1892 Jabber Function monitors the data stream sent to
the Twisted-Pair Transmitter to limit the maximum continuous transmission time as per the ISO/IEC 8802-3
standard. The ISO/IEC specification defines the 10Base-T Jabber activation time limit (that is, the
maximum transmission time) as between 20 ms and 150 ms. The ICS1892 Jabber Function complies with
this specification and has a typical Jabber timer limit of 21 ms. (For more information, see
Section 10.5.19,
“10Base-T: Jabber Timing”
.)
When the Jabber Function detects that the transmission time exceeds the maximum Jabber time limit, the
ICS1892 asserts the Collision Detect (COL) signal. During this ‘jabber de-activation time’, the data stream
is interrupted and kept from reaching the Twisted-Pair Transmitter for a typical time of 324 ms. This time
complies with the ISO/IEC specification of 0.5 ±0.25 sec (that is, from 250 ms to 750 ms). During this time,
when interrupting the data stream and asserting the COL signal, the ICS1892 transmits Normal Link Pulses
and sets the QuickPoll Detailed Status Register’s Jabber Detected bit (bit 17.2) to logic one. This bit is a
latching high (LH) bit. (For more information on latching high and latching low bits, see
Section 8.1.4.1,
“Latching High Bits”
and
Section 8.1.4.2, “Latching Low Bits”
.)
The ICS1892 provides the Station Management entity (STA) with the ability to disable the Jabber Function
with the ICS1892 Jabber Inhibit bit (the 10Base-T Operations Register’s bit 18.5). Setting bit 18.5 to logic:
Zero (the default) implements the ISO/IEC specified function, as described above.
One disables the ISO/IEC specified Jabber Function.
7.5.10
10Base-T Operation: SQE Test
The ICS1892 has a Signal Quality Error (SQE) Test module used exclusively for 10Base-T operations.
When enabled, the ICS1892 performs the SQE Test at the completion of each transmitted packet (that is,
whenever the TX_EN signal transitions from high to low). When TX_EN goes low, an enabled SQE Test
typically delays 630 ns and subsequently asserts the COL signal to the MAC Interface for a typical duration
of 1 μs duration. The ISO/IEC specification for (1) the delay is 10 bit times, ± 5 bit times and for (2) the
duration is from 0.6 to 1.6 μs. The ICS1892 SQE Test Function is:
Enabled only when all the following conditions are true:
– The ICS1892 is in node mode.
– The ICS1892 is in half-duplex mode.
– A valid link is established.
– The 10Base-T Operations Register’s SQE Test Inhibit bit (bit 18.2) is logic zero (the default).
– The TX_EN signal has transitioned from high to low.
Disabled whenever any of the following are true:
– As per the ISO/IEC specification, whenever the ICS1892 is in either of the following modes:
Repeater mode
Full-duplex mode
– As per the ISO/IEC specification, whenever the ICS1892 detects a link failure, it automatically
disables the SQE Test Function.
– The 10Base-T Operations Register’s SQE Test Inhibit bit (bit 18.2) is logic one. [This bit provides the
Station Management entity (STA) with the ability to disable the SQE Test function.]
Note:
1.
2.
In 10Base-T mode, a bit time = 100 ns.
The SQE Test also has the name 10Base-T Heartbeat. For details on the SQE waveforms, see
Section
10.5.18, “10Base-T: Heartbeat Timing (SQE)”
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1892Y-14 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893AF | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893Y-10 | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893 | 3.3-V 10Base-T/100Base-TX Integrated PHYceiver⑩ |
| ICS2002 | Wavedec Digital Audio Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1892Y-14 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893_09 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver? |
| ICS1893AF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AFI | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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