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參數(shù)資料
| 型號： | ICS1572 |
| 英文描述： | GT 7C 7#16S SKT RECP WALL RM |
| 中文描述： | 用戶可編程的差分輸出圖形時鐘發(fā)生器 |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 276K |
| 代理商： | ICS1572 |
Register Mapping - ICS1572-301 (Serial Programming Option)
NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS1572. PC SOFTWARE IS AVAILABLE
FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS.
BIT(S)
BIT REF.
DESCRIPTION
1-3
N1[0]..N1[2]
Sets N1 modulus according to this table. These bits are set to implement
a divide-by-four on power-up.
N1[2]
0
0
0
0
1
1
1
1
N1[1]
0
0
1
1
0
0
1
1
N1[0]
0
1
0
1
0
1
0
1
RATIO
3
4
4
5
6
8
8
10
4
RESERVED
Set to zero.
5
RESERVED
MUST be set to zero.If this bit is ever programmed for a logic one, device
operation will cease and further serial data load into the registers will be
inhibited until a power-off/power-on sequence.
6
JAMPLL
Tristates phase detector outputs, resets phase detector logic, and resets
R, A, M, and N2 counters.
7
DACRST
Set to zero for normal operations. When set to one, the CLK+ output is
kept high and the CLK- output is kept low. (All other device functions are
unaffected.) When returned to zero, the CLK+ and CLK- outputs will
resume toggling on a rising edge of the LD output (+/
1 CLK period).
To initiate a RAMDAC reset sequence, simply write a one to this register
bit followed by a zero.
8
SELXTAL
When set to logic 1, passes the reference frequency to the post-scaler.
9
ALTLOOP
Controls substitution of N1 and N2 dividers into feedback loop of PLL.
When this bit is a logic 1, the N1 and N2 dividers are used.
10
SCEN
VRAM shift clock enable bit. When logic 1, the BLANK pin can be used
to disable the LD/N2 output.
11
EXTFBKEN
External PLL feedback select. When logic 1, the EXTFBK pin is used for
the phase-frequency detector feedback input.
12
PDRSTEN
Phase detector reset enable control bit. When this bit is set, a high level
on the BLANK input will disable PLL locking. See LINE-LOCKED
CLOCK GENERATION section for more details on the operation of
this function.
ICS1572
9
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PDF描述 |
|---|---|
| ICS1572M-101 | GT 4C 4#12 PIN RECP WALL RM |
| ICS1572M-301 | GT 4C 4#12 SKT RECP WALL RM |
| ICS1574B | GT 5C 5#12 PIN RECP WALL RM |
| ICS1574BEB | GT 5C 5#12 SKT RECP WALL RM |
| ICS1574BM | GT 10C 10#16 PIN RECP WALL RM |
相關代理商/技術參數(shù) |
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| ICS1572M101 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
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| ICS1572M301 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS1572M-301 | 制造商:ICS 制造商全稱:ICS 功能描述:User Programmable Differential Output Graphics Clock Generator |
| ICS1574B | 制造商:ICS 制造商全稱:ICS 功能描述:User Programmable Laser Engine Pixel Clock Generator |
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