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參數(shù)資料
| 型號(hào)： | ICS1572 |
| 英文描述： | GT 7C 7#16S SKT RECP WALL RM |
| 中文描述： | 用戶可編程的差分輸出圖形時(shí)鐘發(fā)生器 |
| 文件頁數(shù)： | 15/19頁 |
| 文件大?。?/td> | 276K |
| 代理商： | ICS1572 |
SYMBOL
F
vco
F
xtal
C
par
F
load
T
xhi
T
xlo
T
high
PARAMETER
MIN
20
5
TYP
MAX
160
20
UNITS
MHz
MHz
pF
MHz
ns
ns
%
VCO Frequency (see Note 1)
Crystal Frequency
Crystal Oscillator Loading Capacitance
LOAD Frequency
XTAL1 High Time (when driven externally)
XTAL1 Low TIme (when driven externally)
Differential Clock Output Duty Cycle
(see Note 2)
Differential Clock Output Cumulative
Jitter (see Note 3)
PLL Acquire Time (to within 1%)
VDD Supply Current
VDDO Supply Current (excluding CLK+/-
termination)
20
80
8
8
45
55
J
clk
<0.06
pixel
T
lock
I
dd
I
ddo
500
15
20
μ
s
mA
mA
t.b.d.
t.b.d.
DIGITAL INPUTS - ICS1572-101
1
2
3
4
5
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
STROBE Pulse Width (T
hi
or T
lo
)
10
10
10
10
20
ns
ns
ns
ns
ns
DIGITAL OUTPUTS - ICS1572-301
6
7
8
DATA/HOLD~Setup Time
DATA/HOLD~Hold Time
DATCLK Pulse Width (T
hi
or T
lo
)
10
10
20
ns
ns
ns
PIPELINE DELAY RESET
9
10
11
12
Reset Activation Time
Reset Duration
Restart Delay
Restart Matching
2*Tclk
ns
ns
ns
ns
4*Tload
2*Tload
+1.5*Tclk
-1*Tclk
DIGITAL OUTPUTS
13
14
CLK+/CLK- Clock Rate
LOAD To LD/N2 Skew (Shift Clock Mode)
180
+2
MHz
ns
-2
0
Note 1: Use of the post-divider is required for frequencies lower than 20 MHz on CLK+ & CLK- outputs. Use of the post-divider
is recommended for output frequencies lower than 65 MHz.
Note 2: Using load circuit of Figure 6. Duty cycle measured at zero crossings of difference voltage between CLK+ and CLK-.
Note 3: Cumulative jitter is defined as the maximum error (in the time domain) of any CLK edge, at any point in time, compared
with the equivalent edge generated by an ideal frequency source.
ICS laboratory testing indicates that the typical value shown above can be treated as a maximum jitter specification in
virtually all applications. Jitter performance can depend somewhat on circuit board layout, decoupling, and register
programming.
AC Characteristics
ICS1572
15
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PDF描述 |
|---|---|
| ICS1572M-101 | GT 4C 4#12 PIN RECP WALL RM |
| ICS1572M-301 | GT 4C 4#12 SKT RECP WALL RM |
| ICS1574B | GT 5C 5#12 PIN RECP WALL RM |
| ICS1574BEB | GT 5C 5#12 SKT RECP WALL RM |
| ICS1574BM | GT 10C 10#16 PIN RECP WALL RM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1572M101 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
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| ICS1572M301 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video/Graphics Clock Generator |
| ICS1572M-301 | 制造商:ICS 制造商全稱:ICS 功能描述:User Programmable Differential Output Graphics Clock Generator |
| ICS1574B | 制造商:ICS 制造商全稱:ICS 功能描述:User Programmable Laser Engine Pixel Clock Generator |
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