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參數(shù)資料
| 型號： | ICE3BS02L |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Off-Line SMPS Current Mode Controller with integrated 500V Startup Cell and Latched off Mode |
| 中文描述： | 離線式開關電源電流模式控制器，集成了500V啟動細胞和鎖存關閉模式 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 517K |
| 代理商： | ICE3BS02L |
F3
ICE3BS02L
Functional Description
Version 1.1
10
28 Sep 2005
3.5
Current Limiting
Figure 9
Current Limiting Block
There is a cycle by cycle Current Limiting realized by the
Current-Limit comparator C10 to provide an overcurrent
detection. The source current of the external Power Switch is
sensed via an external sense resistor R
Sense
. By means of
R
Sense
the source current is transformed to a sense voltage
V
Sense
which is fed into the pin CS. If the voltage V
Sense
exceeds the internal threshold voltage V
csth
the comparator
C10 immediately turns off the gate drive by resetting the
PWM Latch FF1. A Propagation Delay Compensation is
added to support the immediate shut down without delay of
the Power Switch in case of Current Limiting. The influence
of the AC input voltage on the maximum output power can
thereby be avoided.
To prevent the Current Limiting from distortions caused by
leading edge spikes a Leading Edge Blanking is integrated in
the current sense path for the comparators C10, C12 and the
PWM-OP.
The output of comparator C12 is activated by the Gate G10
if Active Burst Mode is entered. Once activated the current
limiting is thereby reduced to 0.257V. This voltage level
determines the power level when the Active Burst Mode is
left if there is a higher power demand.
A further comparator C11 is implemented to detect
dangerous current levels which could occur if there is a short
winding in the transformer or the secondary diode is shorten.
To ensure that there is no accidentally entering of the
Latched Mode by the comparator C11 a spike blanking with
190ns is integrated in the output path of comparator C11.
3.5.1
Leading Edge Blanking
Figure 10
Leading Edge Blanking
Each time when the external Power Switch is switched on, a
leading edge spike is generated due to the primary-side
capacitances and secondary-side rectifier reverse recovery
time. This spike can cause the gate drive to switch off
unintentionally. To avoid a premature termination of the
switching pulse, this spike is blanked out with a time
constant of t
LEB
= 220ns. During this time, the gate drive will
not be switched off.
3.5.2
In case of overcurrent detection, the switch-off of the
external Power Switch is delayed due to the propagation
delay of the circuit. This delay causes an overshoot of the
peak current I
peak
which depends on the ratio of dI/dt of the
peak current (see Figure 11).
Propagation Delay Compensation
Figure 11
Current Limiting
The overshoot of Signal2 is bigger than of Signal1 due to the
steeper rising waveform. This change in the slope is
depending on the AC input voltage. Propagation Delay
Compensation is integrated to limit the overshoot
dependency on dI/dt of the rising primary current. That
means the propagation delay time between exceeding the
current sense threshold V
csth
and the switch off of the
external Power Switch is compensated over temperature
C11
Current Limiting
C10
1.66V
C12
&
0.257V
Leading
Edge
Blanking
220ns
G10
Spike
Blanking
190
ns
Propagation-Delay
Compensation
V
csth
Active Burst
Mode
PWM Latch
FF1
10k
D1
1pF
PWM-OP
CS
Latched Off
Mode
t
V
Sense
V
csth
t
LEB
= 220ns
t
I
Sense
I
Limit
t
Propagation Delay
I
Overshoot1
I
peak1
Signal1
Signal2
I
Overshoot2
I
peak2
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