參數(shù)資料
型號(hào): IC62VV25616L-100B
英文描述: 256Kx16 bit 1.8V and Ultra Low Power CMOS Static RAM
中文描述: 256Kx16位1.8V和超低功耗CMOS靜態(tài)RAM
文件頁數(shù): 8/11頁
文件大?。?/td> 321K
代理商: IC62VV25616L-100B
8
Integrated Circuit Solution Inc.
LPSR019-0A 11/13/2001
IC62VV25616L
IC62VV25616LL
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
-55
-70
-100
Symbol
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWB
t
PWE
t
SD
t
HD
t
HZWE
(3)
t
LZWE
(3)
Parameter
Min.
Max.
Min.
Max.
Min.
Max
Unit
Write Cycle Time
55
70
100
ns
CE
to Write End
50
65
80
ns
Address Setup Time to Write End
50
65
80
ns
Address Hold from Write End
0
0
0
ns
Address Setup Time
0
0
0
ns
LB, UB
Valid to End of Write
45
60
80
ns
WE
Pulse Width
45
55
80
ns
Data Setup to Write End
25
30
40
ns
Data Hold from Write End
0
0
0
ns
WE
LOW to High-Z Output
30
30
40
ns
WE
HIGH to Low-Z Output
5
5
5
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 1.4V and output loading specified in
Figure 1.
2. The internal write time is defined by the overlap of
CE
LOW, and
UB
or
LB
, and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCS
t
PWE
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(
CE
Controlled
)
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the
CE
and
WE
inputs and at least
one of the
LB
and
UB
inputs being in the LOW state.
2. WRITE = (
CE
) [ (
LB
) = (
UB
) ] (
WE
).
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