參數(shù)資料
型號: IC42S16800-8TIG
英文描述: ER 14C 14#16 SKT PLUG
中文描述: 4(2)M中的x 8(16)位× 4銀行(128 - Mbit的)同步動態(tài)RAM
文件頁數(shù): 23/69頁
文件大?。?/td> 1118K
代理商: IC42S16800-8TIG
IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
Integrated Circuit Solution Inc.
DR023-0E 6/11/2004
23
Read / Write Command Interval
Read to Read Command Interval
During a read cycle when a new read command is asserted, it will be effective after the
CAS
latency, even if the previous
read operation has not completed. READ will be interrupted by another READ.
Each read command can be asserted in every clock without any restriction.
Write to Write Command Interval
During a write cycle, when a new Write command is asserted, the previous burst will terminate and the new burst will begin
with a new write command. WRITE will be interrupted by another WRITE.
Each write command can be asserted in every clock without any restriction.
READ to READ Command Interval
Burst lengh=4, CAS latency=2
CLK
Command
DQ
QA0
QB2
QB1
QB0
Read A
T0
T1
T2
T3
T4
T5
T6
T7
Hi-Z_
T8
1
cyc
l
e
QB3
Read B
Burst lengh=4, CAS latency=2
CLK
Command
DQ
QA0
QB2
QB1
QB0
Write A
T0
T1
T2
T3
T4
T5
T6
T7
Hi-Z_
T8
1
cyc
l
e
QB3
Write B
WRITE to WRITE Command Interval
相關PDF資料
PDF描述
IC42S16800L-8TIG 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM
IC42S32200 RES 1M-OHM 1% 0.1W 100PPM THICK-FILM SMD-0603 5K/REEL-7IN-PA
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IC42S32202L-8BIG 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM
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