參數(shù)資料
型號(hào): IBMN364404CT3C-260
英文描述: x4 SDRAM
中文描述: x4內(nèi)存
文件頁數(shù): 17/71頁
文件大?。?/td> 1251K
代理商: IBMN364404CT3C-260
IBMN364164
IBMN364404
IBMN364804
64Mb Synchronous DRAM - Die Revision C
19L3265.E35856B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 17 of 71
Non-Minimum Write to Read Interval
COMMAND
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
t
CK2,
DQs
CAS latency = 2
DIN A
0
t
CK3,
DQs
CAS latency = 3
DIN A
0
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Input data for the Write is masked.
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
NOP
DIN A
1
DIN A
1
(Burst Length = 4, CAS latency = 2, 3)
: “H” or “L”
相關(guān)PDF資料
PDF描述
IBMN364404CT3C-360 x4 SDRAM
IBMN364404CT3C-75A x4 SDRAM
IBMN364804CT3C-260 x8 SDRAM
IBMN364804CT3C-360 x8 SDRAM
IBMN364804CT3C-75A x8 SDRAM
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