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參數資料
| 型號： | IBM25NPE405L-3FA200CZ |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PowerNP |
| 中文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA324 |
| 封裝： | 23 X 23 MM, PLASTIC, EBGA-324 |
| 文件頁數： | 49/54頁 |
| 文件大?。?/td> | 460K |
| 代理商： | IBM25NPE405L-3FA200CZ |
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
47
I/O Specifications—133 and 200MHz
(Part 1 of 2)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2.
The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM. Output times in table are in cycle 1.
3. SDRAM I/O timings are specified relative to a SysClk terminated in a lumped 10pF load.
4. SDRAM interface hold times are guaranteed at the NPe405L package pin. System designers must use the NPe405L
IBIS model (available from
www.chips.ibm.com
) to ensure their clock distribution topology minimizes loading and
reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Signal
Input (ns)
Output (ns)
Output Current (mA)
I/O H
(maximum)
Clock
Notes
Setup Time
(T
IS
min)
Hold Time
T
IH
min)
Valid Delay
(T
OV
max)
Hold Time
(T
OH
min)
I/O L
(minimum)
Ethernet Interface
EMC0MDClk
EMC0MDIO
EMC0TxD0:3
[EMC0Tx0:1D0:1]
[EMC0Tx0:1D]
EMC0TxEn
[EMC0Tx0En]
[EMC0Sync]
EMC0TxErr[EMC0Tx1En]
PHY0Col[PHY0Rx1Er]
PHY0CrS[PHY0CrS0DV]
PHY0RxClk
PHY0RxD0:3
[PHY0Rx0:1D0:1]
[PHY0Rx0:1D]
PHY0RxDV[PHY0CRS1DV]
PHY0RxErr[PHY0Rx0Er]
PHY0TxClk[PHY0RefClk]
HDLCEX Interface
HDLCEXRxClk
HDLCEXRxDataA:B
HDLCEXRxFS
HDLCEXTxClk
HDLCEXTxDataA:B
HDLCEXTxFS
[HDLCEXTxEnA]
[HDLCEXTxEnB]]
Trace Interface
[TrcClk]GPIO00
[TS1E]GPIO01
[TS2E]GPIO02
[TS1O]GPIO03
[TS2O]GPIO04
[TS3:6]GPIO05:08
n/a
n/a
n/a
n/a
7.4
8.8
10.5
[7.3]
[5.0]
11.8
[7.2]
[5.6]
11.8[7.4]
n/a
n/a
n/a
1.5
1.2
3.0
[2.3]
[1.7]
2.9
[2.3]
[1.7]
2.9[2.4]
n/a
n/a
n/a
12
12
8
8
1, async
1
EMC0MDClk
n/a
n/a
12
8
PHYTX
1
n/a
n/a
12
8
PHYTX
1
n/a
n/a
12
n/a
n/a
n/a
8
PHYTX
1
1
1
async[0.2]
async[0.1]
n/a
1.5
[0.8]
[0.9]
1.3[0.7]
1.3[0.7]
n/a
async[1.7]
async[1.9]
n/a
1.7
[1.7]
[0.3]
1.7[1.7]
1.8[1.9]
n/a
n/a
n/a
n/a
1, async
n/a
n/a
n/a
n/a
PHYRX
1
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
PHYRX
PHYRX
1
1
1, async
n/a
23.8
24.2
n/a
n/a
20.3
n/a
n/a
n/a
2.1
1.1
n/a
n/a
1.0
n/a
n/a
n/a
n/a
n/a
n/a
10.5
n/a
11.3
11.8
n/a
n/a
n/a
n/a
3.3
n/a
3.5
3.8
n/a
n/a
n/a
n/a
12
n/a
12
12
n/a
n/a
n/a
n/a
8
n/a
8
8
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
11.2
7.0
7.0
6.5
6.4
6.4
1.2
1.2
1.2
1.0
1.0
1.0
12
12
12
12
12
12
8
8
8
8
8
8
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