參數(shù)資料
型號: IBM25NPE405L-3FA133CZ
廠商: APPLIEDMICRO INC
元件分類: 微控制器/微處理器
英文描述: PowerNP
中文描述: 32-BIT, 133 MHz, RISC PROCESSOR, PBGA324
封裝: 23 X 23 MM, PLASTIC, EBGA-324
文件頁數(shù): 12/54頁
文件大?。?/td> 460K
代理商: IBM25NPE405L-3FA133CZ
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
10
IIC Bus Interface
Compliant with Phillips Semiconductors I
2
C Specification, dated 1995
Operation at 100kHz or 400kHz
8-bit data
10- or 7-bit address
Slave transmitter and receiver
Master transmitter and receiver
Multiple bus masters
Supports fixed V
DD
IIC interface
Two independent 4 x 1 byte data buffers
One programmable interrupt request signal
Provides full management of all IIC bus protocol
Programmable error recovery
HDLCEX Interface
32-channel HDLC controller
Two full-duplex Pulse Code Modulation (PCM) Highway ports at speeds up to 4.096 Mbps per port or
8.192 Mbps when using a single port
Supports HDLC protocol as well as a Transparent mode
For a single channel per port, autonomous management of I-Frames and S-Frames of the Normal
Response mode (NRM) protocol on one channel per port. U-frames are handled by software.
Supports software emulation of NRM on all channels
General Purpose IO (GPIO) Controller
Most GPIOs are pin-shared with other functions. Configuration registers are provided to determine
whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. The
GPIO function has 32 I/Os.
Each GPIO output is separately programmable to emulate an open-drain driver (drives to zero, three-
stated if output bit is 1)
Universal Interrupt Controller (UIC)
Two cascaded Universal Interrupt Controllers (UICs) provide the control, status, and communications
necessary for the interrupt sources and the PowerPC processor.
Features include:
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