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參數(shù)資料
| 型號： | IBM25CPC700CB3B66 |
| 英文描述： | Peripheral (Multifunction) Controller |
| 中文描述： | 周邊（多功能）控制器 |
| 文件頁數(shù)： | 24/50頁 |
| 文件大?。?/td> | 516K |
| 代理商： | IBM25CPC700CB3B66 |
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Page 20
Version 1.51
PowerPC 740 and PowerPC 750 Datasheet
5/20/99
PowerPC 740 and PowerPC 750 Embedded Microprocessor
IBM CMOS 0.20 um Copper Technology EMPPC740L and EMPPC750L
IEEE 1149.1 AC Timing Specifications
The table below provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 9, Figure 10,
Figure 11, and Figure 12. The five JTAG signals are; TDI, TDO, TMS, TCK, and TRST.
JTAG AC Timing Specifications (Independent of SYSCLK)
See Table “Recommended Operating Conditions,” on page 7 for operating conditions, C
L
= 50pF.
Num
Characteristic
Min
Max
Unit
Notes
TCK frequency of operation
0
25
MHz
1
TCK cycle time
40
—
ns
2
TCK clock pulse width measured at 1.4V
15
—
ns
3
TCK rise and fall times
0
2
ns
4
4
spec obsolete, intentionally omitted
5
TRST assert time
25
—
ns
1
6
Boundary-scan input data setup time
4
—
ns
2
7
Boundary-scan input data hold time
16
—
ns
2
8
TCK to output data valid
4
20
ns
3, 5
9
TCK to output high impedance
3
19
ns
3, 4
10
TMS, TDI data setup time
0
—
ns
11
TMS, TDI data hold time
15
—
ns
12
TCK to TDO data valid
2.5
12
ns
5
13
TCK to TDO high impedance
3
9
ns
4
Note:
1. TRST is an asynchronous level sensitive signal. Guaranteed by design.
2. Non-JTAG signal input timing with respect to TCK.
3. Non-JTAG signal output timing with respect to TCK.
4. Guaranteed by characterization and not tested.
5. Minimum spec guaranteed by characterization and not tested.
Figure 9. JTAG Clock Input Timing Diagram
1
2
2
3
3
VM = Midpoint Voltage (1.4V)
VM
TCK
VM
VM
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