參數(shù)資料
型號(hào)： HYS72D128520GR-7F-B
廠商： INFINEON TECHNOLOGIES AG
英文描述： Connector Wall Plate; Color:Almond; Leaded Process Compatible:Yes; No. of Ports:2 RoHS Compliant: Yes
中文描述： 注冊(cè)DDR SDRAM內(nèi)存模塊
文件頁(yè)數(shù)： 19/39頁(yè)
文件大?。?/td> 1036K
代理商： HYS72D128520GR-7F-B
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Electrical Characteristics
Data Sheet
19
Rev. 1.03 2004-01
Address and control input setup
time
t
IS
1.1
—
0.9
—
0.9
—
ns
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Address and control input hold
time
t
IH
1.1
—
0.9
—
0.9
—
ns
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Read preamble
Read preamble setup time
Read postamble
Active to Precharge command
Active to Active/Auto-refresh
command period
Auto-refresh to Active/Auto-
refresh command period
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery +
precharge time
Internal write to read command
delay
Exit self-refresh to non-read
command
Exit self-refresh to read
command
Average Periodic Refresh
Interval
t
RPRE
t
RPRES
t
RPST
t
RAS
t
RC
0.9
1.5
0.40 0.60
50
70
1.1
—
0.9
NA
0.40
1.1
0.9
NA
0.40
1.1
—
0.60
120E+3
t
CK
—
t
CK
t
CK
ns
CL > 1.5
2)3)4)5)
2)3)4)5)11)
0.60
120E+3 45
—
2)3)4)5)
120E+3 45
—
2)3)4)5)
65
65
ns
2)3)4)5)
t
RFC
80
—
75
—
75
—
ns
2)3)4)5)
t
RCD
t
RP
t
RAP
t
RRD
20
20
20
15
—
—
—
—
20
20
20
15
—
—
—
—
20
20
20
15
—
—
—
—
ns
ns
ns
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
t
WR
t
DAL
15
—
15
(
t
wr
/
t
CK
) + (
t
rp
/
t
CK
)
—
15
—
ns
t
CK
2)3)4)5)
2)3)4)5)12)
t
WTR
1
—
1
—
1
—
t
CK
CL > 1.5
2)3)4)5)
t
XSNR
80
—
75
—
75
—
ns
2)3)4)5)
t
XSRD
200
—
200
—
200
—
t
CK
2)3)4)5)
t
REFI
—
7.8
—
7.8
—
7.8
μ
s
2)3)4)5)13)
1) 0
°
C
≤
T
A
≤
70
°
C;
V
DDQ
= 2.5 V
±
0.2 V,
V
DD
= +2.5 V
±
0.2 V
2) Input slew rate
≥
1 V/ns for DDR266a, DDR266F and = 1 V/ns for DDR200
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is
V
REF
. CK/CK slew rate are
≥
1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF
stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
t
HZ
and
t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
Table 12
Parameter
AC Timing - Absolute Specifications –8/–7/-7F
Symbol
–8
–7
–7F
Unit Note/
Test
Condition
1)
DDR200
Min. Max.
DDR266A
Min.
DDR266F
Min. Max.
Max.
相關(guān)PDF資料
PDF描述
HYS72D128521GR-7-B Connector Wall Plate; Color:Electric White; Leaded Process Compatible:Yes; No. of Ports:4 RoHS Compliant: Yes
HYS72D32500GR-8-B Registered DDR SDRAM-Modules
HYS72D64500GR-8-B Registered DDR SDRAM-Modules
HYS72T128020HU-37-A 240-Pin Unbuffered DDR2 SDRAM Modules
HYS64T128020HU-37-A 240-Pin Unbuffered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72D128520GR-8 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:x72 SDRAM Module
HYS72D128520GR-8-A 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:?1GB (128Mx72) PC1600 2-bank?
HYS72D128520GR-8-B 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:Low Profile Registered DDR-I SDRAM-Modules
HYS72D128521GR-7-B 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:Low Profile Registered DDR-I SDRAM-Modules
HYS72D128521GR-7F-B 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:Low Profile Registered DDR-I SDRAM-Modules
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*