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參數(shù)資料
| 型號(hào)： | HYS64V64220GBDL |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 144 pin SO-DIMM SDRAM Modules |
| 中文描述： | 144引腳的SO - DIMM內(nèi)存模塊 |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大?。?/td> | 456K |
| 代理商： | HYS64V64220GBDL |
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HYS64V64220GBDL-7/7.5/8-D
144 pin SO-DIMM SDRAM Modules
Infineon Technologies
9
2002-08-06
Notes
1. For proper power-up see the operation section of the component sheet.
2. AC timing tests
for LV-TTL versions
have
V
IL
= 0.4 V and
V
IH
= 2.4 V with the timing referenced to
the 1.4 V crossover point. The transition time is measured between
V
IH
and
V
IL
. All AC
measurements assume
t
T
= 1 ns with the AC output load circuit shown in figure below. Specified
t
AC
and
t
OH
parameters are measured with a 50 pF only, without any resistive termination and
with an input signal of 1V / ns edge rate between 0.8 V and 2.0 V.
3. If clock rising time is longer than 1 ns, a time (
t
T
/2
0.5) ns has to be added to this parameter.
4. If
t
T
is longer than 1 ns, a time (
t
T
1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycles and depend on the operating frequency
of the clock, as follows:
the number of clock cycles = specified value of timing period (counted in
fractions as a whole number)
6. Access time from clock
t
AC
is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time
t
OH
is 1.8 ns for PC133 components with no termination and 0 pF load.
7. It is recommended to use two clock cycles between the last data-in and the precharge command
in case of a write command without Auto-Precharge. One clock cycle between the last data-in
and the precharge command is also supported, but restricted to cycle times tck greater or equal
the specified twr value, where tck is equal to the actual system clock time
8. When a Write command with AutoPrecharge has been issued, a time of tdal(min) has be fullfilled
before the next Activate Command can be applied. For each of the terms, if not already an
integer, round up to the next highest integer. tck is equal to the actual system clock time.
9. All AC characteristics shown are for SDRAM components. An initial pause of 100
μ
s is required
after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh
(CBR) cycles before the Mode Register Set Operation can begin.
10.
AC timing tests have V
il
= 0.4 V and V
ih
= 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between V
ih
and V
il
. All AC measurements assume t
T
=1ns
50 pF
I/O
Measurement conditions for
t
AC
and
t
OH
CLOCK
2.4 V
0.4 V
INPUT
IS
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
IH
t
1.4 V
IO.vsd
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS64V64220GBDL-7-D | 144 pin SO-DIMM SDRAM Modules |
| HYS64V64220GBDL-75-D | 144 pin SO-DIMM SDRAM Modules |
| HYS64V64220GBDL-8-D | 144 pin SO-DIMM SDRAM Modules |
| HYS64V64220GU | 3.3 V 64M x 64/72-Bit, 512MByte SDRAM Modules 168-pin Unbuffered DIMM Modules |
| HYS64V64220GBDL-7.5-D | ?512MB PC133 (2-2-2) 2-bank. FBGA based. available 3Q02? |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS64V64220GBDL-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|64MX64|CMOS|DIMM|144PIN|PLASTIC |
| HYS64V64220GBDL-7.5-C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?512MB PC133 (3-3-3) 2-bank. FBGA based. End-of-Life? |
| HYS64V64220GBDL-7.5-D | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:?512MB PC133 (2-2-2) 2-bank. FBGA based. available 3Q02? |
| HYS64V64220GBDL-75-D | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:144 pin SO-DIMM SDRAM Modules |
| HYS64V64220GBDL-7-D | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:144 pin SO-DIMM SDRAM Modules |
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