參數(shù)資料
型號(hào): HYS64V64220GBDL
廠商: INFINEON TECHNOLOGIES AG
英文描述: 144 pin SO-DIMM SDRAM Modules
中文描述: 144引腳的SO - DIMM內(nèi)存模塊
文件頁數(shù): 11/13頁
文件大?。?/td> 456K
代理商: HYS64V64220GBDL
HYS64V64220GBDL-7/7.5/8-D
144 pin SO-DIMM SDRAM Modules
Infineon Technologies
11
2002-08-06
Serial Presence Detects
A serial presence detect storage device - E
2
PROM - is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E
2
PROM device during module
production using a serial presence detect protocol ( I
2
C synchronous 2-wire bus)
SPD-Table:
Byte#
Description
SPD Entry Value
Hex
64Mx64
-7
64Mx64
-7.5
80
08
04
0D
64Mx64
-8
0
1
2
3
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses
(without BS)
Number of Column Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access time from Clock at
CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
SDRAMwidth,Primary
Error Checking SDRAM data width
Minimum clock delay for back-to-
back random column address
Burst Length supported
Number of SDRAM banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM module attributes
128
256
SDRAM
12
4
5
6
7
8
9
10
2
64
0
0A
02
40
00
01
75
54
LVTTL
7.5ns / 10.0 ns
5.4ns / 6.0 ns
75
54
A0
60
10
11
12
13
14
15
none
00
82
08
00
01
Self-Refresh, 7,6
μ
s
x8
n/a
t
ccd
= 1 CLK
16
17
18
19
20
21
1, 2, 4 & 8
2
2, & 3
CS latency = 0
Write latency = 0
non buffered/non
reg.
VDD tol +/- 10
%
7.5ns / 10.0 ns
5.4ns / 6.0 ns
0F
04
06
01
01
00
22
23
24
SDRAM Device Attributes :General
SDRAM Cycle Time at CL = 2
SDRAM Access Time from Clock at
CL=2
SDRAM Cycle Time at CL = 1
SDRAM Access Time from Clock at
CL=1
Minimum Row Precharge Time
0E
75
54
A0
60
25
26
not supported
not supported
00
00
FF
FF
FF
FF
27
20 ns
0F
14
相關(guān)PDF資料
PDF描述
HYS64V64220GBDL-7-D 144 pin SO-DIMM SDRAM Modules
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參數(shù)描述
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