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參數(shù)資料
| 型號(hào)： | HYS64V16200GU-8B |
| 廠商： | SIEMENS A G |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules |
| 中文描述： | 16M X 64 SYNCHRONOUS DRAM MODULE, 6 ns, DMA168 |
| 封裝： | DIMM-168 |
| 文件頁(yè)數(shù)： | 10/16頁(yè) |
| 文件大?。?/td> | 263K |
| 代理商： | HYS64V16200GU-8B |
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144 pin SO-DIMM SDRAM Modules
HYS64V16200GDL/HYS64V32220GDL
INFINEON Technologies
10
9.01
Notes:
1.
All AC characteristics shown are for SDRAM components.
An initial pause of 100
μ
s is required after power-up, then a Precharge All Banks command must
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can
begin.
2. AC timing tests have V
il
= 0.4 V and V
ih
= 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between V
ih
and V
il
. All AC measurements assume t
T
=1ns
with the AC output load circuit shownSpecified tac and toh parameters are measured with a 50
pF only, without any resistive termination and with a input signal of 1V / ns edge rate between
0.8V and 2.0 V.
.
3. If clock rising time is longer than 1ns, a time (t
T
-0.5) ns has to be added to this parameter.
4. If t
T
is longer than 1ns, a time (t
T
-1) ns has to be added to this parameter.
5. Any time that the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh
commands must be given to
“
wake-up
“
the device.
6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
once the Self Refresh Exit command is registered.
7. Referenced to the time which the output achieves the open circuit condition, not to output voltage
levels.
Serial Presence Detects:
A serial presence detect storage device - E
2
PROM - is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E
2
PROM device during module
production using a serial presence detect protocol ( I
2
C synchronous 2-wire bus)
50 pF
I/O
Measurement conditions for
tac and toh
CLOCK
2.4 V
0.4 V
INPUT
IS
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
IH
t
1.4 V
IO.vsd
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS64V32220GU-8B | 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules |
| HYS64V32300GU-7.5-D | SDRAM|32MX64|CMOS|DIMM|168PIN|PLASTIC |
| HYS64V32300GU | 3.3 V 32M x 64/72-Bit, 256MByte SDRAM Modules 168-pin Unbuffered DIMM Modules |
| HYS64V32300GU-75-C2 | 3.3 V 32M x 64/72-Bit, 256MByte SDRAM Modules 168-pin Unbuffered DIMM Modules |
| HYS64V32300GU-75-D | 3.3 V 32M x 64/72-Bit, 256MByte SDRAM Modules 168-pin Unbuffered DIMM Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS64V1620GCD-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HYS64V1620GCDL-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HYS64V16220GCDL-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HYS64V16220GDL | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:144 pin SO-DIMM SDRAM Modules |
| HYS64V16220GDL-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:144 pin SO-DIMM SDRAM Modules |
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