參數(shù)資料
型號(hào): HYS64D64020GBDL-5-C
廠商: INFINEON TECHNOLOGIES AG
英文描述: 200-Pin Small Outline Dual-In-Line Memory Modules
中文描述: 200引腳小外型雙列直插內(nèi)存模塊
文件頁(yè)數(shù): 6/27頁(yè)
文件大小: 692K
代理商: HYS64D64020GBDL-5-C
Data Sheet
6
Rev. 1.1, 2004-05
200-Pin Small Outline Dual-In-Line Memory Modules
SO-DIMM
HYS64D64020HBDL–5–C
HYS64D64020GBDL–5–C
HYS64D64020HBDL–6–C
HYS64D64020GBDL–6–C
1
Overview
1.1
Features
Non-parity 200-Pin Small Outline Dual-In-Line Memory Modules
Two ranks 64M
×
64 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM)
Single +2.5 V (
±
0.2 V) power supply and Single +2.6V (
±
0.1 V) power supply for DDR400
Built with 256 Mbit DDR SDRAMs organised as
×
8 in P–TFBGA–60 packages
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E
2
PROM
Jedec standard form factor: 67.60 mm
×
31.75 mm
×
3.80 mm
Gold plated contacts
Table 1
Performance
1.2
Description
The HYS64D64020HBDL–5–C and HYS64D64020GBDL–5–C are industry standard 200-Pin Small Outline
Dual-In-Line Memory Modules (SO-DIMMs) organized as 64M
×
64. The memory array is designed with Double
Data Rate Synchronous DRAMs (DDR SDRAM). A variety of decoupling capacitors are mounted on the PC board.
The DIMMs feature serial presence detect based on a serial E
2
PROM device using the 2-pin I
2
C protocol. The first
128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
Notes
1. All part numbers end with a place code designating the silicon-die revision. Reference information available on
request. Example: HYS64D32020GDL-6-B, indicating rev. B dies are used for SDRAM components.
2. The Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the
latencies and SPD code definition (for example “2033
0” means CAS latency of 2.0 clocks, RCD
1)
latency of
3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card
used for this module.
Part Number Speed Code
Speed Grade
–5
DDR400B
PC3200–3033
200
166
133
6
DDR333B
PC2700–2533
166
166
133
Unit
MHz
MHz
MHz
Component
Module
@CL3
@CL2.5
@CL2
max. Clock Frequency
f
CK3
f
CK2.5
f
CK2
1) RCD: Row-Column-Delay
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