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參數(shù)資料
| 型號(hào)： | HYS6472V16200GU |
| 廠商： | SIEMENS AG |
| 英文描述： | Network Cable Assembly; Connector Type A:T568A/B Modular Plug; Connector Type B:T568A/B Modular Plug; Cable Length:15ft; Approval Categories:Augmented Category 6 standards; cord color per TIA/EIA-606 standard RoHS Compliant: Yes |
| 中文描述： | 3.3伏16米x 64/72-Bit SDRAM模組3.3伏32M的x 64/72-Bit SDRAM模組3.3伏6400 x 64/72-Bit SDRAM模組 |
| 文件頁(yè)數(shù)： | 9/17頁(yè) |
| 文件大?。?/td> | 84K |
| 代理商： | HYS6472V16200GU |
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HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
Semiconductor Group
9
1998-08-01
AC Characteristics
T
A
= 0 to 70
°
C;
V
SS
= 0 V;
V
CC
= 3.3 V
±
0.3 V,
t
T
= 1 ns
Parameter
1, 2
Symbol
Limit Values
Unit
Note
-8
PC100-222
-8B
PC100-323
min.
max.
min.
max.
Clock and Clock Enable
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
t
CK
10
10
–
–
10
12
–
–
ns
ns
System Frequency
CAS Latency = 3
CAS Latency = 2
f
CK
–
–
100
100
–
–
100
83
MHz
MHz
Clock Access Time
CAS Latency = 3
CAS Latency = 2
t
AC
–
–
6
6
–
–
6
7
ns
ns
3, 4
Clock High Pulse Width
t
CH
t
CL
t
CS
t
CH
t
CKSP
3
–
3
–
ns
4
Clock Low Pulse Width
3
–
3
–
ns
4
Input Setup Time
2
–
2
–
ns
5
Input Hold Time
1
–
1
–
ns
5
CKE Setup Time
(Power down mode)
2
–
2
–
ns
6
CKE Setup Time
(Self Refresh Exit)
t
CKSR
10
–
–
–
ns
7
Transition Time (rise and fall)
t
T
1
–
–
–
ns
Common Parameters
RAS to CAS Delay
t
RCD
t
RC
t
RAS
t
RP
t
RRD
t
CCD
20
–
20
–
ns
Cycle Time
70
–
70
–
ns
Active Command Period
48
–
48
–
ns
Precharge Time
20
–
30
–
ns
Bank to Bank Delay Time
16
–
20
–
ns
CAS to CAS Delay Time
(same bank)
1
–
1
–
CLK
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