參數(shù)資料
型號(hào): HYS6472V16200GU
廠(chǎng)商: SIEMENS AG
英文描述: Network Cable Assembly; Connector Type A:T568A/B Modular Plug; Connector Type B:T568A/B Modular Plug; Cable Length:15ft; Approval Categories:Augmented Category 6 standards; cord color per TIA/EIA-606 standard RoHS Compliant: Yes
中文描述: 3.3伏16米x 64/72-Bit SDRAM模組3.3伏32M的x 64/72-Bit SDRAM模組3.3伏6400 x 64/72-Bit SDRAM模組
文件頁(yè)數(shù): 14/17頁(yè)
文件大?。?/td> 84K
代理商: HYS6472V16200GU
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
Semiconductor Group
14
1998-08-01
62-61
Superset information
(may be used in future)
FF
FF
FF
FF
62
SPD Revision
Revision 1.2
12
12
12
12
63
Checksum for bytes
0 - 62
64-
125
Manufacturers
information (optional)
(FF
H
if not used)
Frequency Specification
XX
XX
XX
XX
126
100 MHz
64
64
64
64
127
100 MHz support details
AF
AD
AF
AD
128+
Unused storage locations –
FF
FF
FF
FF
SPD-Table for 256MBit SDRAM based PC100 Modules
Byte#
Description
SPD Entry
Value
Hex
64M
×
64
two bank
-8
64M
×
64
two bank
-8B
64M
×
72
two bank
-8
64M
×
72
two bank
-8B
0
Number of SPD bytes
128
80
80
80
80
1
Total bytes in Serial PD
256
08
08
08
08
2
Memory Type
SDRAM
04
04
04
04
3
Number of Row
Addresses
(without BS bits)
13
0D
0D
0D
0D
4
Number of Column
Addresses
(for 32M
×
8 SDRAMs)
Number of DIMM Banks
10
0A
0A
0A
0A
5
2
02
02
02
02
6
Module Data Width
64/72
40
40
48
48
7
Module Data Width
(cont’d)
0
00
00
00
00
8
Module Interface Levels
LVTTL
01
01
01
01
9
SDRAM Cycle Time at
CL = 3
10.0 ns
A0
A0
A0
A0
SPD-Table for 256MBit SDRAM based PC100 Modules
(cont’d)
Byte#
Description
SPD Entry
Value
Hex
32M
×
64
one bank
-8
32M
×
64
one bank
-8B
32M
×
72
one bank
-8
32M
×
72
one bank
-8B
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