參數(shù)資料
型號(hào): HYS64-74V8200GU
廠商: SIEMENS AG
英文描述: Network Cable Assembly; Connector Type A:T568A/B Modular Plug; Connector Type B:T568A/B Modular Plug; Cable Length:10ft; Approval Categories:Augmented Category 6 standards; cord color per TIA/EIA-606 standard RoHS Compliant: Yes
中文描述: 3.3伏8米× 64/72-Bit一銀行內(nèi)存模塊3.3伏16米x 64/72-Bit 2銀行內(nèi)存模塊
文件頁數(shù): 16/17頁
文件大?。?/td> 84K
代理商: HYS64-74V8200GU
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
Semiconductor Group
16
1998-08-01
Byte# Description
SPD Entry Value
Hex
16M
×
64
-10
8M
×
64
-10
8M
×
72
-10
16M
×
72
-10
22
SDRAM Device Attributes:
General
V
CC
tol
±
10%
06
06
06
06
23
Min. Clock Cycle Time at
CAS Latency = 2
15.0 ns
F0
F0
F0
F0
24
Max. data access time from
Clock for CL= 2
9.0 ns
90
90
90
90
25
Minimum Clock Cycle Time
at CL = 1
not supported
FF
FF
FF
FF
26
Maximum Data Access
Time from Clock at CL = 1
not supported
FF
FF
FF
FF
27
Minimum Row Precharge
Time
30 ns
1E
1E
1E
1E
28
Minimum Row Active to
Row Active delay
t
RRD
Minimum RAS to CAS delay
t
RCD
Minimum RAS pulse width
t
RAS
Module Bank Density (per
bank)
20 ns
14
14
14
14
29
30 ns
1E
1E
1E
1E
30
45 ns
2D
2D
2D
2D
31
64 MByte
10
10
10
10
32
SDRAM input setup time
3 ns
30
30
30
30
33
SDRAM input hold time
1 ns
10
10
10
10
34
SDRAM data input hold time 3 ns
30
30
30
30
35
SDRAM data input setup
time
1 ns
10
10
10
10
62-61
Superset information
(may be used in future)
FF
FF
FF
FF
62
SPD Revision
Revision 1.2
12
12
12
12
63
Checksum for bytes 0 - 62
B0
C2
B1
C3
64-
125
Manufacturers information
(optional)
(FF
H
if not used)
Frequency Specification
XX
XX
XX
XX
126
66 MHz
66
66
66
66
127
Details
AF
AF
FF
FF
128+
Unused storage locations
FF
FF
FF
FF
SPD-Table for PC66 Modules
(cont’d)
相關(guān)PDF資料
PDF描述
HYS72V32300GR-75-C2 PC133 Registered SDRAM-Modules
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HYS72V1283201GR-75-C2 PC133 Registered SDRAM-Modules
HYS72V32301GR-75-C2 PC133 Registered SDRAM-Modules
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