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參數(shù)資料
| 型號： | HYS64-74V8200GU |
| 廠商： | SIEMENS AG |
| 英文描述： | Network Cable Assembly; Connector Type A:T568A/B Modular Plug; Connector Type B:T568A/B Modular Plug; Cable Length:10ft; Approval Categories:Augmented Category 6 standards; cord color per TIA/EIA-606 standard RoHS Compliant: Yes |
| 中文描述： | 3.3伏8米× 64/72-Bit一銀行內(nèi)存模塊3.3伏16米x 64/72-Bit 2銀行內(nèi)存模塊 |
| 文件頁數(shù)： | 15/17頁 |
| 文件大?。?/td> | 84K |
| 代理商： | HYS64-74V8200GU |
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
Semiconductor Group
15
1998-08-01
SPD-Table for PC66 Modules
Byte# Description
SPD Entry Value
Hex
16M
×
64
-10
8M
×
64
-10
8M
×
72
-10
16M
×
72
-10
0
Number of SPD bytes
128
80
80
80
80
1
Total bytes in Serial PD
256
08
08
08
08
2
Memory Type
SDRAM
04
04
04
04
3
Number of Row Addresses
(without BS bits)
12
0C
0C
0C
0C
4
Number of Column
Addresses
(for x8 SDRAM)
9
09
09
09
09
5
Number of DIMM Banks
1/2
01
01
02
02
6
Module Data Width
64/72
40
48
40
48
7
Module Data Width (cont’d)
0
00
00
00
00
8
Module Interface Levels
LVTTL
01
01
01
01
9
SDRAM Cycle Time at
CL = 3
10.0 ns
A0
A0
A0
A0
10
SDRAM Access time from
Clock at C L= 3
8.0 ns
80
80
80
80
11
Dimm Config
(Error Det/Corr.)
none/ECC
00
02
00
02
12
Refresh Rate/Type
Self Refresh
15.6
μ
s
×
8
n/a/
×
8
80
80
80
80
13
SDRAM width, Primary
08
08
08
08
14
Error Checking SDRAM
data width
00
08
00
08
15
Minimum clock delay for
back-to-back random
column address
t
CCD
= 1 CLK
01
01
01
01
16
Burst Length supported
1, 2, 4, 8 & full page
8F
8F
8F
8F
17
Number of SDRAM banks
4
04
04
04
04
18
Supported CAS Latencies
CAS latency = 2 & 3
06
06
06
06
19
CS Latencies
CS latency = 0
01
01
01
01
20
WE Latencies
Write latency = 0
01
01
01
01
21
SDRAM DIMM module
attributes
non buffered/
non reg.
00
00
00
00
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