- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄385433 > HYMP112S64MP8-E4 (Hynix Semiconductor Inc.) SCREW LOCKS FEMALE SETS PDF資料下載
參數(shù)資料
| 型號(hào)： | HYMP112S64MP8-E4 |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | SCREW LOCKS FEMALE SETS |
| 中文描述： | DDR2 SDRAM的SO - DIMM插槽 |
| 文件頁(yè)數(shù)： | 7/17頁(yè) |
| 文件大?。?/td> | 405K |
| 代理商： | HYMP112S64MP8-E4 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)
HYMP112S64(L)MP8
Rev. 0.1/ July 2004
7
Input AC Logic Level
AC Input Test Conditions
Notes:
1. Input waveform timing is referenced to the input signal crossing through the V
REF
level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from V
IL(dc)
max to V
IH(ac)
min for rising edges and the
range from V
IH(dc)
min to V
IL(ac)
max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to
VIL(ac) on the negative transitions.
Parameter
Symbol
Min
Max
Unit
Note
AC Input logic High
VIH(AC)
VREF + 0.250
-
V
AC Input logic Low
VIL(AC)
-
VREF - 0.250
V
Symbol
Condition
Value
Units
Notes
V
REF
Input reference voltage
0.5 * V
DDQ
V
1
V
SWING(MAX)
Input signal maximum peak to peak swing
1.0
V
1
SLEW
Input signal minimum slew rate
1.0
V/ns
2, 3
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
V
REF
V
IL(dc)
max
V
IL(ac)
max
V
SS
< Figure : AC Input Test Signal Waveform >
V
SWING(MAX)
delta TR
delta TF
Start of Falling Edge Input Timing
Start of Rising Edge Input Timing
V
IH
(dc)
min -
V
IL
(ac)
max
delta TF
Falling Slew =
Rising Slew = V
IH(ac)
min - V
IL(dc)
max
delta TR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72D64300HBR-5-C | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64300HBR-6-C | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64300HBR-7-C | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64320 | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64320HBR-5-C | 184-Pin Registered Double Data Rate SDRAM Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYMP112U64CP8-C4 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
| HYMP112U64CP8-S5 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
| HYMP112U64CP8-S6 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
| HYMP112U64CP8-Y5 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
| HYMP112U64CR8-C4 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。