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參數(shù)資料
| 型號： | HYB39S512400AT |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512-Mbit Synchronous DRAM |
| 中文描述： | 512兆位同步DRAM |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 718K |
| 代理商： | HYB39S512400AT |
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HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Pin Configuration
Data Sheet
10
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
2
Pin Configuration
2.1
Signal Pin Description
Table 3
Pin
CLK
Signal Pin Description
Type
Signal Polarity Function
Input
Pulse
Positive
Edge
Clock Input
The system clock input. All of the SDRAM inputs are sampled on the rising
edge of the clock.
Clock Enable
Activates the CLK signal when high and deactivates the CLK signal when
low, thereby initiating either the Power Down mode, Suspend mode, or the
Self Refresh mode.
Chip Select
CS enables the command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new
commands are ignored but previous operations continue.
Command Signals
When sampled at the positive rising edge of the clock, CAS, RAS, and WE
define the command to be executed by the SDRAM.
Address Inputs
During a Bank Activate command cycle, A0-A12 define the row address
(RA0-RA12) when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An define the column address
(CA0-CAn) when sampled at the rising clock edge. CAn depends upon the
SDRAM organization:
64M x4
SDRAM CAn = CA9, CA11 (Page Length = 2048 bits)
32M x8
SDRAM CAn = CA9 (Page Length = 1024 bits)
16M x16 SDRAM CAn = CA8 (Page Length = 512 bits)
In addition to the column address, A10 (= AP) is used to invoke the
autoprecharge operation at the end of the burst read or write cycle. If A10
is high, autoprecharge is selected and BA0, BA1 defines the bank to be
precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in conjunction
with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all
four banks will be precharged regardless of the state of BA0 and BA1. If
A10 is low, then BA0 and BA1 are used to define which bank to precharge.
Bank Select
Bank Select Inputs. Bank address inputs selects which of the four banks a
command applies to.
Data Input/Output
Data Input/Output pins operate in the same manner as on EDO or FPM
DRAMs.
CKE
Input
Level
Active
High
CS
Input
Pulse
Active
Low
RAS
CAS
WE
A0 - A12
Input
Pulse
Active
Low
Input
Level
–
BA0, BA1 Input
Level
–
DQx
Input
Output
Level
–
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB39S512400ATL | 512-Mbit Synchronous DRAM |
| HYB39S64160BT-7.5 | Safety Goggle; Pack Quantity:1 RoHS Compliant: NA |
| HYB39S64160BT-8 | Safety Goggle; Pack Quantity:1 RoHS Compliant: NA |
| HYB39S64400BT-7.5 | Faceshield Kit RoHS Compliant: NA |
| HYB39S64400BT-8 | Replacement Visor RoHS Compliant: NA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB39S512400AT-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:512-Mbit Synchronous DRAM |
| HYB39S512400AT-7.5 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:512-Mbit Synchronous DRAM |
| HYB39S512400AT-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:512-Mbit Synchronous DRAM |
| HYB39S512400ATL | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:512-Mbit Synchronous DRAM |
| HYB39S512800AE-7.5 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:512-Mbit Synchronous DRAM |
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