參數(shù)資料
型號: HYB39S256400DT
廠商: INFINEON TECHNOLOGIES AG
英文描述: 256 MBit Synchronous DRAM
中文描述: 256兆位同步DRAM
文件頁數(shù): 17/22頁
文件大?。?/td> 564K
代理商: HYB39S256400DT
INFINEON Technologies
17
2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Operating Currents
T
A
= 0 to 70
o
C; V
SS
= 0 V; V
DD
, V
DDQ
= 3.3 V
±
0.3 V
Parameter & Test Condition
Symb.
-6
-7
-7.5
-8
Note
max.
Operating Current
One bank active, Burst length = 1
t
RC
= t
,
Io = 0 mA
IDD1
100
80
80
80
mA
3, 4
Precharge Standby Current
in Power Down Mode
CS =VIH (min.),
CKE
<
=Vil(max)
IDD2P
2
2
2
2
mA
3
Precharge Standby Current
in Non-Power Down Mode
CS = VIH (min.),
CKE
>
=Vih(min)
IDD2N
35
30
30
25
mA
3
No Operating Current
active state ( max. 4 banks)
CS = VIH(min),
CKE
>
=VIH(min.)
IDD3N
40
35
35
30
mA
3
CS = VIH(min),
CKE
<
=VIL(max.)
IDD3P
5
5
5
5
mA
3
Burst Operating Current
Read command cycling
IDD4
110
90
90
70
mA
3, 4
Auto Refresh Current
Auto Refresh command cycling
t
RFC
= t
RFC(min)
t
RFC
= 7.8
μ
s
IDD5
220
190
190
160
mA
5
3
3
3
3
mA
Self Refresh Current
(standard components)
Self Refresh Mode, CKE=0.2V,
tck=infinity
x4, x8
x16
IDD6
3
1.5
3
1.5
3
1.5
3
1.5
mA
mA
Self Refresh Current
(low power components)
Self Refresh Mode, CKE=0.2V,
tck=infinity
x8, x16
IDD6
0.85
0.85
0.85
0.85
mA
Notes:
3. These parameters depend on the cycle rate. All values are measured at 166 MHz for “-6”, at 133 MHz for
“-7” and “-7.5” and at 100 MHz for “-8” components with the outputs open. Input signals are changed once
during tck.
4. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3
and BL=4 is assumed and the VDDQ current is excluded.
5.
t
RFC
= t
RFC(min)
“burst refresh”, t
RFC
= 7.8
μ
s “distributed refresh”.
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