參數(shù)資料
型號(hào): HYB39S256400DT-75
廠商: INFINEON TECHNOLOGIES AG
英文描述: 256 MBit Synchronous DRAM
中文描述: 256兆位同步DRAM
文件頁數(shù): 20/22頁
文件大?。?/td> 564K
代理商: HYB39S256400DT-75
INFINEON Technologies
20
2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Notes
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests
for LV-TTL versions
have
V
IL
= 0.4 V and
V
IH
= 2.4 V with the timing referenced to
the 1.4 V crossover point. The transition time is measured between
V
IH
and
V
IL
. All AC
measurements assume
t
T
= 1 ns with the AC output load circuit shown in figure below. Specified
t
AC
and
t
OH
parameters are measured with a 50 pF only, without any resistive termination and
with an input signal of 1V / ns edge rate between 0.8 V and 2.0 V.
3. If clock rising time is longer than 1 ns, a time (
t
T
/2
0.5) ns has to be added to this parameter.
4. If
t
T
is longer than 1 ns, a time (
t
T
1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycles and depend on the operating frequency
of the clock, as follows:
the number of clock cycles = specified value of timing period (counted in fractions as a whole
number)
6. Access time from clock
t
AC
is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time
t
OH
is 1.8 ns for PC133 components with no termination and 0 pF load.
7. It is recommended to use two clock cycles between the last data-in and the precharge command
in case of a write command without Auto-Precharge. One clock cycle between the last data-in
and the precharge command is also supported, but restricted to cycle times tck greater or equal
the specified twr value, where tck is equal to the actual system clock time
8. When a Write command with AutoPrecharge has been issued, a time of tdal(min) has be fullfilled
before the next Activate Command can be applied. For each of the terms, if not already an
integer, round up to the next highest integer. tck is equal to the actual system clock time.
50 pF
I/O
Measurement conditions for
t
AC
and
t
OH
CLOCK
2.4 V
0.4 V
INPUT
IS
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
IH
t
1.4 V
IO.vsd
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