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參數(shù)資料
| 型號： | HYB39S256400DCL-75 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256 MBit Synchronous DRAM |
| 中文描述： | 256兆位同步DRAM |
| 文件頁數(shù)： | 9/22頁 |
| 文件大?。?/td> | 564K |
| 代理商： | HYB39S256400DCL-75 |
INFINEON Technologies
9
2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
DQM
LDQM
UDQM
Input
Pulse
Active
High
The Data Input/Output mask places the DQ buffers in a
high impedance state when sampled high. In Read mode,
DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM
has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the
write operation if DQM is high.
One DQM input is present in x4 and x8 SDRAMs, LDQM
and UDQM controls the lower and upper bytes in x16
SDRAMs.
V
DD
V
SS
Supply –
–
Power and ground for the input buffers and the core logic.
V
DDQ
V
SSQ
Supply –
–
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
Pin
Type
Signal Polarity Function
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB39S256400DCL-8 | 256 MBit Synchronous DRAM |
| HYB39S256400DT | 256 MBit Synchronous DRAM |
| HYB39S256400DT-6 | 256 MBit Synchronous DRAM |
| HYB39S256400DT-7 | 256 MBit Synchronous DRAM |
| HYB39S256400DT-75 | 256 MBit Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB39S256400DCL-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-MBit Synchronous DRAM |
| HYB39S256400DT | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 MBit Synchronous DRAM |
| HYB39S256400DT-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-MBit Synchronous DRAM |
| HYB39S256400DT-7 | 制造商:Infineon Technologies AG 功能描述: |
| HYB39S256400DT-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256Mb (64Mx4) PC133 3-3-3? |
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