參數(shù)資料
型號(hào)： HYB39S256400DCL-6
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256-MBit Synchronous DRAM
中文描述： 256兆位同步DRAM
文件頁(yè)數(shù)： 24/28頁(yè)
文件大?。?/td> 630K
代理商： HYB39S256400DCL-6
(
t
WR
/
t
CK
) + (
t
RP
/
t
CK
)
HYB39S256[40/80/16]0D[C/T](L)
256-MBit Synchronous DRAM
Electrical Characteristics
Data Sheet
24
Rev. 1.02, 2004-02
10072003-13LE-FGQQ
Refresh Cycle
Refresh Period (8192 cycles)
Self Refresh Exit Time
Data Out Hold Time
t
REF
t
SREX
t
OH
–
1
3
64
—
—
–
1
3
64
—
—
–
1
3
64
—
—
–
1
2.5
64
—
—
ms
CLK
ns
3)5)
Read Cycle
Data Out to Low Impedance Time
t
LZ
Data Out to High Impedance
Time
DQM Data Out Disable Latency
0
3
—
8
0
3
—
7
0
3
—
7
0
3
—
6
ns
ns
t
HZ
t
DQZ
—
2
—
2
—
2
—
2
CLK
Write Cycle
Last Data Input to Precharge
(Write without AutoPrecharge)
Last Data Input to Activate
(Write with AutoPrecharge)
DQM Write Mask Latency
t
WR
15
—
15
—
14
—
12
—
ns
8)
t
DAL(min.)
CLK
9)
t
DQW
0
—
0
—
0
—
0
—
CLK
1)
T
A
= 0 to 70
°
C;
V
SS
= 0 V;
V
DD
,
V
DDQ
= 3.3 V ± 0.3 V,
t
T
= 1 ns
2) For proper power-up see the operation section of this data sheet.
3) AC timing tests for LV-TTL versions have
V
IL
= 0.4 V and
V
IH
= 2.4 V with the timing referenced to the 1.4 V crossover point.
The transition time is measured between
V
IH
and
V
IL
. All AC measurements assume
t
T
= 1 ns with the AC output load circuit
shown in figure below. Specified
t
AC
and
t
OH
parameters are measured with a 50 pF only, without any resistive termination
and with an input signal of 1V / ns edge rate between 0.8 V and 2.0 V.
4) If clock rising time is longer than 1 ns, a time (
t
T
/2 - 0.5) ns has to be added to this parameter.
5)
Access time from clock
t
AC
is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time
t
OH
is 1.8 ns for PC133 components with no termination and 0 pF load.
6) If
t
T
is longer than 1 ns, a time (
t
T
- 1) ns has to be added to this parameter.
7) These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing period (counted in fractions as a whole number)
8) It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command
without Auto-Precharge. One clock cycle between the last data-in and the precharge command is also supported, but
restricted to cycle times tck greater or equal the specified twr value, where tck is equal to the actual system clock time.
9) When a Write command with AutoPrecharge has been issued, a time of
t
DAL(min)
has be fullfilled before the next Activate
Command can be applied. For each of the terms, if not already an integer, round up to the next highest integer.
t
CK
is equal
to the actual system clock time.
Table 15
Parameter
AC Timing - Absolute Specifications –8/-7.5/–7/-6
(cont’d)
1)2)3)
Symbol
–8
–7.5
PC166 -
333
min. max.
–7
–6
Unit Notes
PC100 -
222
min. max.
PC166 -
222
min. max.
PC166 -
333
min. max
.
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