參數(shù)資料
型號(hào)： HYB39S16320TQ-10
廠商： SIEMENS A G
元件分類： DRAM
英文描述： 128 x 64 pixel format, LED Backlight available
中文描述： 512K X 32 SYNCHRONOUS GRAPHICS RAM, PQFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 5/70頁(yè)
文件大小： 563K
代理商： HYB39S16320TQ-10
HYB 39S16320TQ-6/-7/-8
Semiconductor Group
5
1998-10-01
Signal Pin Description
Pin
Type
Signal Polarity Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SGRAM inputs are
sampled on the rising edge of the clock.
CKE
Input
Level
Active
High
Activates the CLK signal when high and deactivates the
CLK signal when low. By deactivating the clock, CKE low
initiates the Power Down mode, Suspend mode, or the Self
Refresh mode.
CS
Input
Pulse
Active
Low
CS enables the command decoder when low and disables
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.
RAS
CAS
WE
Input
Pulse
Active
Low
When sampled at the positive rising edge of the clock,
CAS, RAS, and WE define the operation to be executed by
the SGRAM.
A0 - A9
Input
Level
–
During a Bank Activate command cycle, A0-A9 defines the
row address (RA0-RA9) when sampled at the rising clock
edge.
During a Read or Write command cycle, A0-A7 defines the
column address (CA0-CA7) when sampled at the rising
clock edge.
In addition to the column address, CA8 is used to invoke
autoprecharge operation at the end of the burst read or
write cycle. If A8 is high, autoprecharge is selected and BA
defines the bank to be precharged (low = bank A,
high bank B). If A8 is low, autoprecharge is disabled.
During a Precharge command cycle, A8 is used in
conjunction with BA to control which bank(s) to precharge.
If A8 is high, both bank A and bank B will be precharged
regardless of the state of BA. If A8 is low, then BA is used
to define which bank to precharge.
BA
Input
Level
–
Selects which bank is activated. BA low selects bank A and
BA high selects bank B.
DQ0 -
DQ31
Input
Output
Level
–
Data Input/Output pins operate in the same manner as on
conventional DRAMs, with the exception of the Block Write
function. In this case, the DQx pins perform a masking
operation.
相關(guān)PDF資料
PDF描述
HYB39S16400-1 16 MBit Synchronous DRAM
HYB39S16400CT-8 16 MBit Synchronous DRAM
HYB39S16800CT-8 16 MBit Synchronous DRAM
HYB39S16400BT-10 JOYSTICK, POTENTIOMETER, 3 AXIS; Angle:20(degree); Centres, fixing:32.2mm; Depth, external:41.5mm; Diameter, panel cut-out:39mm; Length / Height, external:73mm; Material:ABS; Operations, mechanical No. of:1000000; Power, DC:0.125W; RoHS Compliant: Yes
HYB39S16400CT-10 16 MBit Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB39S16320TQ-5.5 制造商:Siemens 功能描述:Electronic Component
HYB39S16320TQ-6 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Special Mode Registers Two color registers Burst Read with Single Write Operation
HYB39S16320TQ-7 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Special Mode Registers Two color registers Burst Read with Single Write Operation
HYB39S16320TQ-8 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Special Mode Registers Two color registers Burst Read with Single Write Operation
HYB39S1632TQ55 制造商:N/A 功能描述:NEW
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*