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參數(shù)資料
| 型號： | HYB25R288180C-845 |
| 英文描述： | DRAM|RAMBUS|16MX18|CMOS|BGA|66PIN|PLASTIC |
| 中文描述： | 內(nèi)存| Rambus公司| 16MX18 |的CMOS | BGA封裝| 66PIN |塑料 |
| 文件頁數(shù)： | 57/76頁 |
| 文件大小： | 1218K |
| 代理商： | HYB25R288180C-845 |
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2002-05-06
Page 57 of 76
HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
IDD Current Measurement Conditions
IDD1 : Operating current : One bank operation
1. Only one bank is accessed with t
RC(min)
, Burst Mode, Address and Control inputs on
N
OP edge are changing once
per clock cycle. l
out
= 0 mA
2. Timing patterns
-
DDR200
(100Mhz, CL=2) : tCK = 10 ns, CL=2, BL=4, tRCD = 2
*
tCK, tRAS = 5
*
tCK
Setup: A0
N
R0
N N
P0
N
Read : A0
N
R0
N N
P0
N
- repeat the same timing with random address changing
50
%
of data changing at every burst
-
DDR266A
(133Mhz, CL=2) : tCK = 7.5 ns, CL=2, BL=4, tRCD = 3
*
tCK, tRC =
9 *
tCK, tRAS = 5
*
tCK
Setup: A0
N N
R0
N
P0
N N N
Read : A0
N N
R0
N
P0
N NN
- repeat the same timing with random address changing
50
%
of data changing at every burst
-
DDR333
(166Mhz, CL=2.5) : tCK = 6 ns, CL=2.5, BL=4, tRCD = 3
*
tCK, tRC =
9 *
tCK, tRAS = 5
*
tCK
Setup: A0
N N
R0
N
P0
N N N
Read : A0
N N
R0
N
P0
N N N
- repeat the same timing with random address changing
50
%
of data changing at every burst
3.Legend : A=Activate, R=Read,
W
=
W
rite, P=Precharge,
N
=
N
OP
IDD7 : Operating current: Four bank operation
1. Four banks are being interleaved with t
RC(min)
, Burst Mode, Address and Control inputs on
N
OP edge are not
changing. l
out
= 0 mA
2. Timing patterns
-
DDR200
(100Mhz, CL=2) : tCK = 10 ns, CL=2, BL=4, tRRD = 2
*
tCK, tRCD= 3
*
tCK, Read with autoprecharge
Setup: A0
N
A1 R0 A2 R1 A3 R2
Read : A0 R3 A1 R0 A2 R1 A3 R2- repeat the same timing with random address changing
50
%
of data changing at every burst
-
DDR266A
(133Mhz, CL=2) : tCK = 7.5 ns, CL=2, BL=4, tRRD = 2
*
tCK, tRCD = 3
*
tCK
Setup: A0
N
A1 R0 A2 R1 A3 R2
N
R3
Read : A0
N
A1 R0 A2 R1 A3 R2
N
R3 - repeat the same timing with random address changing
50
%
of data changing at every burst
-
DDR333
(166Mhz, CL=2.5) : tCK = 6 ns, CL=2.5, BL=4, tRRD = 2
*
tCK, tRCD = 3
*
tCK
Setup: A0
N
A1 R0 A2 R1 A3 R2
N
R3
Read : A0
N
A1 R0 A2 R1 A3 R2
N
R3 - repeat the same timing with random address changing
50
%
of data changing at every burst
3.Legend : A=Activate, R=Read,
W
=
W
rite, P=Precharge,
N
=
N
OP
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