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| 型號： | HYB25L512160AC-7.5 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | BJAWBMSpecialty DRAMs Mobile-RAM |
| 中文描述： | BJAWBMSpecialty DRAM的移動RAM |
| 文件頁數(shù)： | 15/50頁 |
| 文件大?。?/td> | 1335K |
| 代理商： | HYB25L512160AC-7.5 |
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HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
Data Sheet
15
Rev. 1.3, 2004-04
10212003-BSPE-77OL
3.2.1.2
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in
Table 5
.
Burst Type
3.2.1.3
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability
of the first piece of output data. The latency can be programmed to 2 or 3 clocks.
If a READ command is registered at clock edge
n
, and the latency is
m
clocks, the data will be available with clock
edge
n
+
m
(for details please refer to the READ command description).
CAS Latency
3.2.1.4
When A9 = 0, the burst length programmed via A0-A2 applies to both read and write bursts; when A9 = 1, write
accesses consist of single data elements only.
Write Burst Mode
3.2.2
The Extended Mode Register controls additional low power features of the device. These include the Partial Array
Self Refresh (PASR) and the Temperature Compensated Self Refresh (TCSR). The Extended Mode Register is
programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored
information until it is programmed again or the device loses power. The Extended Mode Register must be loaded
when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation.
Violating either of these requirements result in unspecified operation.
Extended Mode Register
Figure 6
Extended Mode Register Definition
Address bits A0-A2 specify the Partial Array Self Refresh (PASR) and bits A3-A4 the Temperature Compensated
Self Refresh (TCSR), while bits A5-A12 shall be written to zero.
A4
A3
TCSR
0
0
70°C
0
1
45°C
1
0
15°C
A2
A1
A0
PASR
0
0
0
all banks
0
0
1
1/2 array (BA1 = 0)
0
1
0
1/4 array (BA1 = BA0 = 0)
0
1
1
Reserved
1
0
0
Reserved
1
0
1
1/8 array
(BA1 = BA0 = RA12 = 0)
1
1
0
1/8 array
(BA1 = BA0 = RA12 = RA11 = 0)
1
1
1
Reserved
BA1 BA0 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
1
0
0
0
0
0
0
0
0
0
TCSR
PASR
Mode Register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25L512160AC | 512MBit Mobile-RAM |
| HYB25M128160C | 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM) |
| HYB25R128160C | 128-MBit Direct RDRAM(128 M位直接RDRAM) |
| HYB 25M144180C | 144-MBit Direct RDRAM(144 M位直接RDRAM) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
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