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參數(shù)資料
| 型號： | HYB25D512400AT-8 |
| 英文描述： | ?512Mb (128Mx4) DDR200 (2-2-2) ? |
| 中文描述： | ？的512Mb（128Mx4）DDR200（2-2-2）？ |
| 文件頁數(shù)： | 25/76頁 |
| 文件大?。?/td> | 1218K |
| 代理商： | HYB25D512400AT-8 |
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2002-05-06
Page 25 of 76
HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Data from any Read burst may be truncated with a Burst Terminate command, as shown on
Terminating a
Read Burst: CAS Latencies (Burst Length = 8)
on page 26. The Burst Terminate latency is equal to the read
(CAS) latency, i.e. the Burst Terminate command should be issued x cycles after the Read command, where
x equals the number of desired data element pairs.
Data from any Read burst must be completed or truncated before a subsequent
W
rite command can be
issued. If truncation is necessary, the Burst Terminate command must be used, as shown on
Read to Write:
CAS Latencies (Burst Length = 4 or 8)
on page 27. The example is shown for t
DQSS
(min). The t
DQSS
(max)
case, not shown here, has a longer bus idle time. t
DQSS
(min) and t
DQSS
(max) are defined in the section on
W
rites.
A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that
Auto Precharge was not activated). The Precharge command should be issued x cycles after the Read com-
mand, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch archi-
tecture). This is shown on
Read to Precharge: CAS Latencies (Burst Length = 4 or 8)
on page 28 for Read
latencies of 2 and 2.5. Following the Precharge command, a subsequent command to the same bank cannot
be issued until t
RP
is met.
N
ote that part of the row precharge time is hidden during the access of the last data
elements.
In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as
described above) provides the same operation that would result from the same Read burst with Auto Pre-
charge enabled. The disadvantage of the Precharge command is that it requires that the command and
address busses be available at the appropriate time to issue the command. The advantage of the Precharge
command is that it can be used to truncate bursts.
相關PDF資料 |
PDF描述 |
|---|---|
| HYB25D512800AT-6 | ?512Mb (64Mx8) DDR333 (2.5-3-3)? |
| HYB25D512800AT-7 | ?512Mb (64Mx8) DDR266A (2-3-3)? |
| HYB25D512800AT-8 | ?512Mb (64Mx8) DDR200 (2-2-2)? |
| HYB25M128160C-653 | RAMBUS DRAM |
| HYB25M128160C-745 | RAMBUS DRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D512400BR-7 | 制造商:Infineon Technologies AG 功能描述:128M X 4 DDR DRAM MODULE, P66 Pin Plastic SMT |
| HYB25D512400CE-5 | 制造商:Infineon Technologies AG 功能描述: |
| HYB25D512800CE-5 | 功能描述:IC DDR SDRAM 512MBIT 66TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應商設備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB25D512800CE-6 | 功能描述:IC DDR SDRAM 512MBIT 66TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應商設備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB25DC512160CE-5 | 制造商:Infineon Technologies AG 功能描述: 制造商:QIMONDA 功能描述: |
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