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參數(shù)資料
| 型號(hào)： | HYB25D256400BT-8 |
| 英文描述： | ?256Mbit (64Mx4) DDR200 (2-2-2)? |
| 中文描述： | ？的256Mbit（64Mx4）DDR200（2-2-2）？ |
| 文件頁數(shù)： | 60/76頁 |
| 文件大?。?/td> | 1218K |
| 代理商： | HYB25D256400BT-8 |
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HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Page 60 of 76
2002-05-06
t
RFC
Auto-refresh to Active/Auto-refresh command
period
80
75
72
ns
1-4
t
RCD
Active to Read or
W
rite delay
20
20
18
ns
1-4
t
RP
Precharge command period
20
20
18
ns
1-4
t
RAP
Active to Autoprecharge delay
20
20
18
ns
1-4
t
RRD
Active bank A to Active bank B command
15
15
12
ns
1-4
t
W
R
W
rite recovery time
15
15
15
ns
1-4
t
DAL
Auto precharge write recovery
+
precharge time
(twr/tck)
+
(trp/tck)
t
CK
1-4,
9
t
W
TR
Internal write to read command delay
1
1
1
t
CK
1-4
t
X
S
N
R
E
xit self-refresh to non-read command
80
75
75
ns
1-4
t
X
SRD
E
xit self-refresh to read command
200
200
200
t
CK
1-4
t
R
E
FI
Average Periodic Refresh Interval (40
9
6 refresh
commands per 64ms refresh period)
15.6
15.6
15.6
μ
s
1-4, 8
1. Input slew rate
>
= 1V/ns for DDR266
&
DDR333 and = 1V/ns for DDR200.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for
signals other than CK/CK, is V
R
E
F.
CK/CK slew rate are
>
= 1.0 V/ns
3. Inputs are not recognized as valid until V
R
E
F
stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (
N
ote 3) is V
TT
.
5. t
HZ
and t
L
Z
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a spe-
cific voltage level, but specify when the device is no longer driving (
HZ
), or begins driving (L
Z
).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (
H
I
GH
, LO
W
, or some point on a valid transition) on or before this CK edge. A valid
transition is defined as monotonic and meeting the input slew rate specifications of the device.
W
hen no writes were previously in
progress on the bus, DQS will be transitioning from
H
i-
Z
to logic LO
W
. If a previous write was in progress, DQS could be
H
I
GH
,
LO
W
, or transitioning from
H
I
GH
to LO
W
at this time, depending on t
DQSS
.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9
. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
10. These parameters guarantee device timing, but they are not necessarily tested on each device
11. Fast slew rate
>
= 1.0 V/ns , slow slew rate
>
= 0.5 V/ns and
<
1V/ns for command/address and CK
&
CK slew rate
>
1.0 V/ns, mea-
sured between VO
H
(ac) and VOL(ac)
Electrical Characteristics & AC Timing - Absolute Specifications
(0
°
C
≤
T
A
≤
70
°
C
;
V
DDQ
= 2.5V
±
0.2V; V
DD
= 2.5V
±
0.2V, See AC Characteristics)
(Part 2 of 2)
Symbol
Parameter
DDR200
-8
DDR266A
-7
DDR333
-6
Unit
N
otes
Min
Max
Min
Max
Min
Max
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25D256400T-7 | DDR Synchronous DRAM |
| HYB25D256400T-7.5 | DDR Synchronous DRAM |
| HYB25D256400T-8 | DDR Synchronous DRAM |
| HYB25D256800AT-7 | ?256Mbit (32Mx8) DDR266A (2-3-3)? |
| HYB25D256800AT-7.5 | DDR Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D256400BTL-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B |
| HYB25D256400BTL-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM |
| HYB25D256400BTL-7F | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM |
| HYB25D256400BTL-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B |
| HYB25D256400CC-5 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit Double-Data-Rate SDRAM |
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