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參數(shù)資料
| 型號： | HYB25D256400AT-8 |
| 英文描述： | ?256Mbit (64Mx4) DDR 200 (2-2-2) End-of-Life? |
| 中文描述： | ？的256Mbit（64Mx4）的DDR 200（2-2-2）結(jié)束的生命？ |
| 文件頁數(shù)： | 19/76頁 |
| 文件大?。?/td> | 1218K |
| 代理商： | HYB25D256400AT-8 |
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2002-05-06
Page 1
9
of 76
HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Reads
Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts
are initiated with a Read command, as shown on
Read Command
on page 20.
The starting column and bank addresses are provided with the Read command and Auto Precharge is either
enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts pre-
charge at the completion of the burst, provided t
RAS
has been satisfied. For the generic Read commands
used in the following illustrations, Auto Precharge is disabled.
During Read bursts, the valid data-out element from the starting column address is available following the
CAS latency after the Read command.
E
ach subsequent data-out element is valid nominally at the next posi-
tive or negative clock edge (i.e. at the next crossing of CK and CK). Page
Read Burst: CAS Latencies (Burst
Length = 4)
on page 21 shows general timing for each supported CAS latency setting. DQS is driven by the
DDR SDRAM along with output data. The initial low state on DQS is known as the read preamble; the low
state coincident with the last data-out element is known as the read postamble. Upon completion of a burst,
assuming no other commands have been initiated, the DQs goes
H
igh-
Z
. Data from any Read burst may be
concatenated with or truncated with data from a subsequent Read command. In either case, a continuous
flow of data can be maintained. The first data element from the new burst follows either the last element of a
completed burst or the last desired data element of a longer burst which is being truncated. The new Read
command should be issued x cycles after the first Read command, where x equals the number of desired
data element pairs (pairs are required by the 2n prefetch architecture). This is shown on
Consecutive Read
Bursts: CAS Latencies (Burst Length = 4 or 8)
on page 22. A Read command can be initiated on any clock
cycle following a previous Read command.
N
onconsecutive Read data is illustrated on
Non-Consecutive
Read Bursts: CAS Latencies (Burst Length = 4)
on page 23. Full-speed Random Read Accesses: CAS
Latencies (Burst Length = 2, 4 or 8) within a page (or pages) can be performed as shown on page 24.
t
RCD
and t
RRD
Definition
RO
W
ACT
N
OP
COL
RO
W
BA y
BA y
BA x
ACT
N
OP
N
OP
CK
CK
Command
A0-A11
BA0, BA1
Don’t Care
RD/
W
R
W
R
t
RCD
t
RRD
N
OP
N
OP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25D256400BC-7 | ?256Mb (64Mx4) FBGA DDR266A (2-3-3)? |
| HYB25D256400BT-6 | ?256Mbit (64Mx4) DDR333 (2.5-3-3)? |
| HYB25D256400BT-7 | ?256Mbit (64Mx4) DDR266A (2-3-3)? |
| HYB25D256400BT-8 | ?256Mbit (64Mx4) DDR200 (2-2-2)? |
| HYB25D256400T-7 | DDR Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D256400B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM |
| HYB25D256400BC-5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM |
| HYB25D256400BC-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM |
| HYB25D256400BC-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B |
| HYB25D256400BC-7F | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B |
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