- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370782 > HYB18T256324F-20 (INFINEON TECHNOLOGIES AG) 256-Mbit GDDR3 DRAM [600MHz] PDF資料下載
參數(shù)資料
| 型號(hào)： | HYB18T256324F-20 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256-Mbit GDDR3 DRAM [600MHz] |
| 中文描述： | 256兆GDDR3顯示內(nèi)存[600MHz的] |
| 文件頁數(shù)： | 20/80頁 |
| 文件大?。?/td> | 2026K |
| 代理商： | HYB18T256324F-20 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
Data Sheet
20
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
2.4.2
If there is more than one bank activated in the Graphics
SDRAM, some commands can be performed in parallel
due to the chip’s multibank architecture. The following
table defines for which commands such a scheme is
possible. All other transitions are illegal. Notes 1-11
define the start and end of the actions belonging to a
Function Truth Table for more than one Activated Bank
submitted command. This table is based on the
assumption that there are no other actions ongoing on
bank n or bank m. If there are any actions ongoing on a
third bank t
RRD
, t
RTW
and t
WTR
have to be taken always
into account.
1. Action ACTIVATE starts with issuing the command
and ends after t
RCD
2. Action WRITE starts with issuing the command and
ends t
WR
after the first pos. edge of CLK following
the last falling WDQS edge; exept for READ,
READ/A. WRITE, WRITE/A ends
t
WTR
after the first
pos. edge of CLK following the last falling WDQS
edge.
3. Action WRITE/A starts with issuing the command
and ends t
WR
after the first positive edge of CLK
following the last falling WDQS edge; exept for
READ, READ/A. WRITE, WRITE/A ends t
WTR
after
the first pos. edge of CLK following the last falling
WDQS edge.
4. Action READ starts with issuing the command and
ends with the first positive edge of CLK following the
last falling edge of RDQS
5. Action READ/A starts with issuing the command
and ends with the first positive edge of CLK
following the last falling edge of RDQS
6. Action PRECHARGE and PRECHARGE ALL start
with issuing the command and ends after t
RP
7. During POWER DOWN and SELF REFRESH only
the EXIT commands are allowed
8. Action AUTO REFRESH starts with issuing the
command and ends after t
RFC
9. Actions MODE REGISTER SET and EXTENDED
MODE REGISTER SET start with issuing the
command and ends after t
MRD
10.Action POWER DOWN EXIT starts with issuing the
command and ends after t
XPN
11.Action SELF REFRESH EXIT starts with issuing the
command and ends after t
XSC
12.During action ACTIVATE an ACT command on
another bank is allowed considering t
RRD
, a PRE
command on another bank is allowed any time.
WR, WR/A, RD and RD/A are always allowed.
13.During action WRITE an ACT or a PRE command
on another bank is allowed any time. A new WR or
WR/A command on another bank must be
separated by at least one NOP from the ongoing
WRITE. RD or RD/A are not allowed before t
WTR
is
met.
Table 7
Current
State
ACTIVE
Function Truth Table I
ongoing action on bank n
possible action in parallel on bank m
ACTIVATE
1
WRITE
2
WRITE/A
3
READ
4
READ/A
5
PRECHARGE
6
PRECHARGE ALL
6
POWER DOWN ENTRY
7
ACTIVATE
1
POWER DOWN ENTRY
7
AUTO REFRESH
8
SELF REFRESH ENTRY
7
MODE REGISTER SET (MRS)
9
EXTENDED MRS
9
POWER DOWN EXIT
10
SELF REFRESH EXIT
11
ACT, PRE, WRITE, WRITE/A, READ, READ/A
12
ACT, PRE, WRITE, WRITE/A, READ, READ/A
13
ACT, PRE, WRITE, WRITE/A, READ
14
ACT, PRE, WRITE, WRITE/A, READ, READ/A
15
ACT, PRE, WRITE, WRITE/A, READ, READ/A
15
ACT, PRE, WRITE, WRITE/A, READ, READ/A
12
-
-
ACT
-
-
-
-
-
-
-
IDLE
POWER DOWN
SELF REFRESH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB18T256324F-22 | 256-Mbit GDDR3 DRAM [600MHz] |
| HYB18T256400AFL-3 | 256 Mbi t DDR2 SDRAM |
| HYB18T256160A-3S | 256 Mbi t DDR2 SDRAM |
| HYB18T256800AFL-3 | 256 Mbi t DDR2 SDRAM |
| HYB18T256400AFL-37 | 256 Mbi t DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
| HYB18T256800AF-5 | 制造商:Infineon Technologies AG 功能描述: |
| HYB18T512161BF-25 | 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA |
| HYB18T512400AF-5 | 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。