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| 型號： | HYB18T1G800C4F-3 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.45 ns, PBGA60 |
| 封裝： | GREEN, PLASTIC, TFBGA-60 |
| 文件頁數(shù)： | 46/58頁 |
| 文件大?。?/td> | 1898K |
| 代理商： | HYB18T1G800C4F-3 |
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HYB18T1G[40/80/16]0C4F
1-Gbit Double-Data-Rate-Two SDRAM
Internet Data Sheet
Rev. 1.01, 2008-11
50
04212008-66HT-ZLFE
7.4
ODT AC Electrical Characteristics
This chapter describes the ODT AC electrical characteristics.
TABLE 41
ODT AC Characteristics and Operating Conditions for DDR2–667 and DDR2–800
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
t
AOND
ODT turn-on delay
2
n
CK
1)
1) New units, “
t
CK.AVG” and “nCK”, are introduced in DDR2-667 and DDR2-800 Unit “tCK.AVG” represents the actual tCK.AVG of the input clock
under operation. Unit “
n
CK” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, “
t
CK” is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
be registered at
T
m + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER.MIN.
t
AON
ODT turn-on
t
AC.MIN
t
AC.MAX +0.7
ns
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from
t
AOND, which is interpreted differently per speed bin. For DDR2-667/800 tAOND is
2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
t
AONPD
ODT turn-on (Power-Down Modes)
t
AC.MIN +2
2
t
CK + tAC.MAX +1
ns
t
AOFD
ODT turn-off delay
2.5
n
CK
t
AOF
ODT turn-off
t
AC.MIN
t
AC.MAX +0.6
ns
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from
t
AOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK.AVG = 3 ns is assumed,
t
AOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by
counting the actual input clock edges.
t
AOFPD
ODT turn-off (Power-Down Modes)
t
AC.MIN + 2
2.5
t
CK + tAC.MAX +1
ns
t
ANPD
ODT to Power Down Mode Entry Latency
3
—
n
CK
t
AXPD
ODT Power Down Exit Latency
8
—
n
CK
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