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參數(shù)資料
| 型號： | HYB18T1G800C4F-3 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.45 ns, PBGA60 |
| 封裝： | GREEN, PLASTIC, TFBGA-60 |
| 文件頁數(shù)： | 39/58頁 |
| 文件大?。?/td> | 1898K |
| 代理商： | HYB18T1G800C4F-3 |
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HYB18T1G[40/80/16]0C4F
1-Gbit Double-Data-Rate-Two SDRAM
Internet Data Sheet
Rev. 1.01, 2008-11
44
04212008-66HT-ZLFE
Examples: 1) If the system provides
t
HP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides
t
HP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
26)
t
QHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
27) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85
°C
and 95
°C.
28) 0 °C
≤
T
CASE ≤ 85 °C.
29) 85
°C <
T
CASE ≤ 95 °C.
30) A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between
any Refresh command and the next Refresh command is 9 x
t
REFI.
31)
t
RPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(
t
RPST), or begins driving (tRPRE). Figure 8 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (
t
RPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
32) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
JIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
JIT.PER.MIN = – 72 ps
and
t
JIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+
t
JIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
JIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
JIT.DUTY.MIN = – 72 ps
and
t
JIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+
t
JIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
34) For these parameters, the DDR2 SDRAM device is characterized and verified to support
t
nPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support
t
nRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which
t
RP = 15 ns, the device will support
t
nRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
35)
t
WTR is at lease two clocks (2 x tCK) independent of operation frequency.
FIGURE 8
Method for Calculating Transitions and Endpoint
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