參數(shù)資料
型號: HY62V16100LR2-I-12
廠商: HYNIX SEMICONDUCTOR INC
元件分類: SRAM
英文描述: 128K X 8 STANDARD SRAM, 120 ns, PDSO44
封裝: 0.400 INCH, REVERSE, TSOP2-44
文件頁數(shù): 8/10頁
文件大?。?/td> 151K
代理商: HY62V16100LR2-I-12
HY62V16100-(I)/HY62U16100-(I) Series
Rev.07 /Jan.99
8
WRITE CYCLE 2 (Note 5)
tDW
tWHZ
WE
Data Valid
tDH
tWP
tAS
Data In
tWR
tCW
tAW
(6)
(7)
tWHZ
ADDR
CS
Data
Out
tWC
Notes:
1. A write occurs during the overlap(tWP) of a low /CS and low /WE .
2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the /WE
transition, outputs remain in a high impedance state.
5. /OE is continuously low(/OE=V
IL
)
6. Q(data out) is the same phase with the write data of this write cycle.
7. Q(data out) is the read data of the next address.
8. If /CS is low during this period, I/O pins are in the output state.
Then the data input signals of opposite phase to the outputs must not be applied to them.
9. Transition is measured +200mV from steady state.
This parameter is sampled and not 100% tested.
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