參數(shù)資料
型號: HY62UF16804B-DFC
廠商: Hynix Semiconductor Inc.
英文描述: 512Kx16bit full CMOS SRAM
中文描述: 512Kx16bit充分的CMOS的SRAM
文件頁數(shù): 8/10頁
文件大小: 197K
代理商: HY62UF16804B-DFC
HY62UF16804B
Notes:
1. A write occurs during the overlap of a low / WE, a low /CS and low /UB and /or /LB.
2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured +200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC
T
A
= 0
°
C to 70
°
C / -40
°
C to 85
°
C
Symbol
Parameter
Test Condition
/CS > Vcc - 0.2V or
/UB=/LB > Vcc-0.2V,
V
IN
> Vcc-0.2V or
V
IN
< Vss+0.2V
Vcc=1.5V, /CS > Vcc - 0.2V or
/UB=/LB > Vcc-0.2V,
V
IN
> Vcc-0.2V or
V
IN
< Vss+0.2V
Chip Deselect to Data
Retention Time
TR
Operating Recovery Time
Notes:
1. Typical values are under the condition of T
A
= 25
°
C .
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM
VCC
DATA RETENTION MODE
Rev.01/Mar. 2002
7
Min
Typ
Max
Unit
V
DR
Vcc for Data Retention
1.2
-
3.3
V
I
CCDR
Data Retention Current
LL
-
1.0
6
uA
TCDR
0
-
-
ns
See Data Retention Timing Diagram
tRC
(2)
-
-
ns
/CS or
/UB & /LB
VDR
/CS>Vcc-0.2V or
/UB=/LB > Vcc-0.2V
tCDR
tR
Vss
2.7V
VIH
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