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參數(shù)資料
| 型號： | HY5V58BLF |
| 英文描述： | 32Mx8|3.3V|8K|H/8/P/S|SDR SDRAM - 256M |
| 中文描述： | 32Mx8 | 3.3 | 8K的| H/8/P/S |特別提款權的SDRAM - 256M |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 236K |
| 代理商： | HY5V58BLF |
Rev. 0.2/Jun 02 6
HY5V52CF
DC CHARACTERISTICS II
(DC operating conditions unless otherwise noted)
Note :
1.I
DD1
and I
DD4
depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY5V52CF-8/P/S
4.HY5V52CL:F-8/P/S
Parameter
Symbol
Test Condition
speed
Unit
Note
-8
-P
S
Operating Current
IDD1
Burst length=1, One bank active
t
RC
≥
t
RC
(min), I
OL
=0mA
tbd
tbd
tbd
mA
1
Precharge Standby
Current
in power down mode
IDD2P
CKE
≤
V
IL
(max), t
CK
= 10ns
tbd
mA
IDD2PS
CKE
≤
V
IL
(max), t
CK
=
∞
tbd
Precharge Standby
Current
in non power down mode
IDD2N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CK
= 10ns
Input signals are changed one time during
2clks. All other pins
≥
VDD-0.2V or
≤
0.2V
tbd
mA
IDD2NS
CKE
≥
V
IH
(min), t
CK
=
∞
Input signals are stable.
tbd
Active Standby Current
in power down mode
IDD3P
CKE
≤
V
IL
(max), t
CK
= 10ns
tbd
mA
IDD3PS
CKE
≤
V
IL
(max), t
CK
=
∞
tbd
Active Standby Current
in non power down mode
IDD3N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CK
= 10ns
Input signals are changed one time during
2clks. All other pins
≥
V
DD
-0.2V or
≤
0.2V
tbd
mA
IDD3NS
CKE
≥
V
IH
(min), t
CK
=
∞
Input signals are stable.
tbd
Burst Mode Operating
Current
IDD4
t
t
CK
≥
t
CK
(min), I
OL
=0mA
All banks active
CL=3
tbd
tbd
tbd
mA
1
CL=2
-
tbd
tbd
Auto Refresh Current
IDD5
t
RC
≥
t
RC
(min), All banks active
tbd
tbd
tbd
mA
2
Self Refresh Current
IDD6
CKE
≤
0.2V
tbd
mA
3
tbd
4
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