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參數(shù)資料
| 型號： | HY5PS1G831F-E4 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 1Gb DDR2 SDRAM |
| 中文描述： | 128M X 8 DDR DRAM, 0.5 ns, PBGA68 |
| 封裝： | FBGA-68 |
| 文件頁數(shù)： | 14/33頁 |
| 文件大?。?/td> | 540K |
| 代理商： | HY5PS1G831F-E4 |
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Rev. 1.2 / Dec 2006
14
1
HY5PS1G431(L)F
1
HY5PS1G831(L)F
Note 5: The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as
measured from AC to AC. This is guaranteed by design and characterization.
Note 6: This represents the step size when the OCD is near 18 ohms at nominal conditions across all process cor-
ners/variations and represents only the DRAM uncertainty. A 0 ohm value(no calibration) can only be achieved if the
OCD impedance is 18 ohms +/- 0.75 ohms under nominal conditions.
Output Slew rate load:
Note 7: DRAM output slew rate specification applies to 400MT/s & 533MT/s speed bins.
Note 8: Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in
tDQSQ and tQHS specification.
VTT
25 ohms
Output
(Vout)
Reference
point
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| HY5PS1G831F-Y5 | 1Gb DDR2 SDRAM |
| HY5PS1G831F-Y6 | 1Gb DDR2 SDRAM |
| HY5PS1G831LF | 1Gb DDR2 SDRAM |
| HY5PS1G831LF-C4 | 1Gb DDR2 SDRAM |
| HY5PS1G831LF-C5 | 1Gb DDR2 SDRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HY5PS1G831F-Y5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831F-Y6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831LF | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831LF-C4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831LF-C5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
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