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參數(shù)資料
| 型號： | HY5DV281622DT |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 128M(8Mx16) GDDR SDRAM |
| 中文描述： | 128M的（8M × 16位）GDDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 24/31頁 |
| 文件大?。?/td> | 294K |
| 代理商： | HY5DV281622DT |
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Rev. 0.5 / Aug. 2003
24
HY5DV281622DT
DC CHARACTERISTICS II
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
Parameter
Symbol
Test Condition
Speed
Unit
Note
33
36
4
5
6
Operating Current
IDD0
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and
DQS inputs changing twice per clock cycle;
address and control inputs changing once
per clock cycle
150
140
130
120
100
mA
Operating Current
I
DD1
One bank; Active - Read - Precharge;
Burst=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once
per clock cycle; IOUT=0mA
170
150
140
130
110
mA
Precharge Power
Down Standby
Current
I
DD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
20
mA
Idle Standby Current
I
DD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs
changing once per clock cycle.
VIN=VREF for DQ, DQS and DM
90
80
70
60
50
mA
Active Power Down
Standby Current
I
DD3P
One bank active; Power down mode ;
CKE=Low, tCK=tCK(min)
20
mA
Active Standby
Current
I
DD3N
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per
clock cycle; Address and other control inputs
changing once per clock cycle
90
80
70
60
50
mA
Operating Current
I
DD4R
Burst=2; Reads; Continuous burst; One
bank active; Address and control inputs
changing once per clock cycle;
tCK=tCK(min); IOUT=0mA
250
230
210
180
160
mA
Operating Current
I
DD4W
Burst=2; Writes; Continuous burst; One
bank active; Address and control inputs
changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
210
190
170
150
140
mA
Auto Refresh Current
I
DD5
tRC=tRFC(min); All banks active
220
200
180
150
140
mA
Self Refresh Current
I
DD6
CKE=<0.2V; External clock on;
tCK=tCK(min)
2
mA
Operating Current -
Four Bank Operation
I
DD7
Four bank interleaving with BL=4
350
330
310
270
250
mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5DV281622DT-33 | 128M(8Mx16) GDDR SDRAM |
| HY5DV281622DT-36 | 128M(8Mx16) GDDR SDRAM |
| HY5DV281622DT-4 | 128M(8Mx16) GDDR SDRAM |
| HY5DV281622DT-5 | 128M(8Mx16) GDDR SDRAM |
| HY5DV281622DT-6 | 128M(8Mx16) GDDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DV281622DT-33 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
| HY5DV281622DT-36 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
| HY5DV281622DT-4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
| HY5DV281622DT-5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
| HY5DV281622DT-6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
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