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參數(shù)資料
| 型號： | HY5DU28822BT-X |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 128M-S DDR SDRAM |
| 中文描述： | 128M的，擰DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 23/33頁 |
| 文件大?。?/td> | 343K |
| 代理商： | HY5DU28822BT-X |
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HY5DU28422B(L)T
HY5DU28822B(L)T
Rev. 0.3/May. 02
23
DC CHARACTERISTICS II
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
32Mx4
/
16Mx8
Parameter
Symbol
Test Condition
Speed
Unit Note
-J
-M
-K
-H
-L
Operating Current
IDD0
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and
DQS inputs changing twice per clock cycle;
address and control inputs changing once
per clock cycle
90
80
80
80
80
mA
Operating Current
I
DD1
One bank; Active - Read - Precharge;
Burst=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once
per clock cycle
110
100
100
100
80
mA
Precharge Power
Down Standby
Current
I
DD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
20
15
15
15
15
mA
Idle Standby Current
I
DD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs
changing once per clock cycle.
VIN=VREF for DQ, DQS and DM
40
35
35
35
30
mA
Active Power Down
Standby Current
I
DD3P
One bank active; Power down mode ;
CKE=Low, tCK=tCK(min)
20
20
20
20
20
mA
Active Standby
Current
I
DD3N
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per
clock cycle; Address and other control inputs
changing once per clock cycle
40
40
40
40
40
mA
Operating Current
I
DD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
IOUT=0mA
230
190
190
190
150
mA
Operating Current
I
DD4W
Burst=2; Writes; Continuous burst; One
bank active; Address and control inputs
changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
230
190
190
190
150
mA
Auto Refresh Current
I
DD5
tRC=tRFC(min) - 8*tCK for DDR200 at
100Mhz, 10*tCK for DDR266A & DDR266B at
133Mhz; distributed refresh
160
150
150
150
140
mA
Self Refresh Current
I
DD6
CKE=<0.2V; External clock on;
tCK=tCK(min)
Normal
2
2
2
2
2
mA
Low Power
1
1
1
1
1
mA
Operating Current -
Four Bank Operation
I
DD7
Four bank interleaving with BL=4, Refer to
the following page for detailed test condition
300
260
260
260
220
mA
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU28822DLT | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb-S DDR SDRAM |
| HY5DU28822DLT-X | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb-S DDR SDRAM |
| HY5DU28822DT | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb-S DDR SDRAM |
| HY5DU28822DT-X | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb-S DDR SDRAM |
| HY5DU28822ETP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb DDR SDRAM |
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