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參數(shù)資料
| 型號： | HY5DS573222F |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 256M(8Mx32) GDDR SDRAM |
| 中文描述： | 256M（8Mx32）GDDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 326K |
| 代理商： | HY5DS573222F |
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1
HY5DS573222F(P)
Rev. 1.0 / Feb. 2005
5
PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
CK, /CK
Input
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
level after Vdd is applied.
/CS
Input
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-
mands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied.
A0 ~ A11
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A8 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).
/RAS, /CAS, /WE
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
DM0 ~ DM3
Input
Input Data Mask: DM(0~3) is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is sam-
pled on both edges of DQS. Although DM pins are input only, the DM loading matches the
DQ and DQS loading. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the
data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the
data on DQ24-Q31.
DQS0 ~ DQS3
I/O
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. DQS0 corresponds to the data on
DQ0-Q7; DQS1 corresponds to the data on DQ8-Q15; DQS2 corresponds to the data on
DQ16-Q23; DQS3 corresponds to the data on DQ24-Q31
DQ0 ~ DQ31
I/O
Data input / output pin : Data Bus
V
DD
/V
SS
Supply
Power supply for internal circuits and input buffers.
V
DDQ
/V
SSQ
Supply
Power supply for output buffers for noise immunity.
V
REF
Supply
Reference voltage for inputs for SSTL interface.
NC
NC
No connection.
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| HY5DS573222F-28 | 256M(8Mx32) GDDR SDRAM |
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| HY5DS573222F-36 | 256M(8Mx32) GDDR SDRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| HY5DS573222F-28 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M(8Mx32) GDDR SDRAM |
| HY5DS573222F-33 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M(8Mx32) GDDR SDRAM |
| HY5DS573222F-36 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M(8Mx32) GDDR SDRAM |
| HY5DS573222F-4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M(8Mx32) GDDR SDRAM |
| HY5DS573222FP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M(8Mx32) GDDR SDRAM |
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