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參數(shù)資料
| 型號： | HY57W2A1620HCLT-S |
| 英文描述： | SDRAM|4X2MX16|CMOS|TSOP|54PIN|PLASTIC |
| 中文描述： | 內(nèi)存| 4X2MX16 |的CMOS |的TSOP | 54PIN |塑料 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 221K |
| 代理商： | HY57W2A1620HCLT-S |
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T
HY5W26CF / HY57W281620HCT
Rev. 1.2 / Nov. 01
4
BALL DESCRIPTION
Note. Please find HY5xxxxxxT Series for standard 54TSOP-II pin configuration & description.
BALL OUT
SYMBOL
TYPE
DESCRIPTION
F2
CLK
INPUT
Clock : The system clock input. All other inputs are registered
to the SDRAM on the rising edge of CLK
Clock Enable : Controls internal clock signal and when deacti-
vated, the SDRAM will be one of the states among power
down, suspend or self refresh
Chip Select : Enables or disables all inputs except CLK, CKE,
UDQM and LDQM
Bank Address : Selects bank to be activated during RAS activ-
ity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
F3
CKE
INPUT
G9
CS
INPUT
G7,G8
BA0, BA1
INPUT
H7, H8, J8, J7,
J3, J2, H3, H2,
H1, G3, H9, G2
F8, F7, F9
A0 ~ A11
INPUT
RAS, CAS,
WE
UDQM,
LDQM
DQ0 ~
DQ15
INPUT
Command Inputs : RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask:Controls output buffers in read mode and masks
input data in write mode
Data Input/Output:Multiplexed data input/output pin
F1, E8
INPUT
A8, B9, B8, C9,
C8, D9, D8, E9,
E1, D2, D1, C2,
C1, B2, B1, A2
A9, E7, J9, A1,
E3, J1
A7, B3, C7, D3,
A3, B7, C3, D7
E2, G1
I/O
VDD/VSS
SUPPLY
Power supply for internal circuits
VDDQ/
VSSQ
NC
SUPPLY
Power supply for output buffers
-
No connection
相關(guān)PDF資料 |
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|---|---|
| HY57W2A1620HCST-B | x16 SDRAM |
| HY57W2A1620HCST-H | SDRAM|4X2MX16|CMOS|TSOP|54PIN|PLASTIC |
| HY57W2A1620HCST-P | x16 SDRAM |
| HY57W2A1620HCST-S | SDRAM|4X2MX16|CMOS|TSOP|54PIN|PLASTIC |
| HY5W26CF-P | x16 SDRAM |
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