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參數(shù)資料
| 型號： | HY57W2A1620HCLT-S |
| 英文描述： | SDRAM|4X2MX16|CMOS|TSOP|54PIN|PLASTIC |
| 中文描述： | 內(nèi)存| 4X2MX16 |的CMOS |的TSOP | 54PIN |塑料 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 221K |
| 代理商： | HY57W2A1620HCLT-S |
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T
HY5W26CF / HY57W281620HCT
Rev. 1.2 / Nov. 01
20
AC CHARACTERISTICS
I
(AC operating conditions unless otherwise noted)
Note : 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to
the parameter.
2. Access time to be measured with input signals of 1v/ns edge rate, from 0.8v to 0.2v. If tR > 1ns, then
(tR/2-0.5)ns should be added to the parameter.
Parameter
Symbol
H
P
S
B
Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
System Clock
Cycle Time
CAS Latency=3
tCK3
7.5
1000
10
1000
10
1000
15
1000
ns
CAS Latency=2 tCK2
10
10
3
3
12
3
3
-
-
3
2
1
2
1
2
1
2
1
1
3
3
15
3.5
-
3.5
-
-
-
3
2
1
2
1
2
1
2
1
1
3
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock High Pulse Width
tCHW
2.5
-
2.5
-
-
-
2.7
-
1.5
-
0.8
-
1.5
-
0.8
-
1.5
-
0.8
-
1.5
-
0.8
-
1
2.7
5.4
3
2.7
7
-
-
6
6
-
-
-
-
-
-
-
-
-
-
6
6
-
-
6
6
-
-
-
-
-
-
-
-
-
-
6
6
1
1
2
Clock Low Pulse Width
tCLW
Access Time From
Clock
CAS Latency=3
tAC3
5.4
-
6
9
9
-
-
-
-
-
-
-
-
-
-
9
9
CAS Latency=2
tAC2
-
3
2
1
2
1
2
1
2
1
1
Data-out Hold Time
tOH
Data-Input Setup Time
tDS
1
1
1
1
1
1
1
1
Data-Input Hold Time
tDH
Address Setup Time
tAS
Address Hold Time
tAH
CKE Setup Time
tCKS
CKE Hold Time
tCKH
Command Setup Time
tCS
Command Hold Time
tCH
CLK to Data Output in Low-Z Time
tOLZ
-
CLK to Data Output
in High-Z Time
CAS Latency=3 tOHZ3
CAS Latency=2 tOHZ2
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY57W2A1620HCST-B | x16 SDRAM |
| HY57W2A1620HCST-H | SDRAM|4X2MX16|CMOS|TSOP|54PIN|PLASTIC |
| HY57W2A1620HCST-P | x16 SDRAM |
| HY57W2A1620HCST-S | SDRAM|4X2MX16|CMOS|TSOP|54PIN|PLASTIC |
| HY5W26CF-P | x16 SDRAM |
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